EP9307-IR Cirrus Logic Inc, EP9307-IR Datasheet

IC Universal Platform ARM9 SOC Prcessor

EP9307-IR

Manufacturer Part Number
EP9307-IR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-IR

Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1255

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Price
Part Number:
EP9307-IR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Part Number:
EP9307-IRZ
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Cirrus Logic Inc
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Part Number:
EP9307-IRZR
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Cirrus Logic Inc
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Cirrus Logic, Inc.
http://www.cirrus.com
Errata: EP9307 - Silicon Revision: E2
Reference EP9307 Data Sheet revision DS667PP4 dated March 2005.
Determining the Silicon Revision of the Integrated Circuit
AC’97
On the front of the integrated circuit, directly under the part number, is an alpha-numeric line. Characters 5
and 6 in this line represent the silicon revision of the chip. For example, this line indicates that the chip is a
“E2” revision chip:
This Errata is applicable only to the E2 revision of the chip.
Please refer to AN273,
additional information.
Description
Disabling audio transmit by clearing the TEN bit in one of the AC97TXCRx registers will not clear out any
remaining bytes in the TX FIFO. If the number of bytes left in the FIFO is not equal to a whole sample or
samples, this will throw off subsequent audio playback causing distortion or channel swapping.
Workaround
To stop audio playback, do the following:
1) Pause DMA
2) Poll the AC97SRx register until either TXUE or TXFE is set.
3) Clear the TEN bit.
This ensures that the TX FIFO is empty before the transmit channel is disabled.
“EP93xx Rev E Design Guidelines”
Copyright © Cirrus Logic, Inc. 2007
EFWAE2AM0340
(All Rights Reserved)
(Cirrus Logic document AN273REV3) for
ER667E2B
APR ‘07

Related parts for EP9307-IR

EP9307-IR Summary of contents

Page 1

... Errata: EP9307 - Silicon Revision: E2 Reference EP9307 Data Sheet revision DS667PP4 dated March 2005. Determining the Silicon Revision of the Integrated Circuit On the front of the integrated circuit, directly under the part number alpha-numeric line. Characters 5 and 6 in this line represent the silicon revision of the chip. For example, this line indicates that the chip is a “ ...

Page 2

Analog Touch Screen Description After power-on-reset, PENSTS in AR_SETUP2 register has the correct default value of “0”. But after the first touch on the screen, PENSTS is stuck at “1” regardless if the screen is pressed or not. Workaround Configure ...

Page 3

HDLC Description When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of ...

Page 4

Raster EP9312 User's Guide Update As designed, horizontal clock and data are not aligned. Where horizontal clock gating is required, set HACTIVESTRTSTOP equal to HCLKSTRTSTOP+5. Description 1 If the raster engine is using single scan mode, two and two thirds ...

Page 5

USB Description 1 USB clock divider logic operates at a maximum rate of 288MHz under worst case conditions. Workaround When using USB, make sure the clock frequency supplied to the USB clock divider does not exceed 288MHz. The clock supplied ...

Page 6

TM MaverickCrunch Various MaverickCrunch errata share common features. The individual descriptions will refer to these common features. 1) For several errata, an instruction appears in the coprocessor pipeline, but does not execute for one of the following reasons ...

Page 7

Description 1 Under certain circumstances, data in coprocessor registers or in memory may be corrupted. The following sequence of instructions will cause the corruption: 1) Let the first instruction be both: - any coprocessor instruction that is not executed - ...

Page 8

Workaround The simplest workaround is to insure that no two such instructions ever appear in the instruction stream consecutively. Specifically, a conditional coprocessor instruction should not precede a load/store 64/double. Simply inserting another ARM or coprocessor instruction accomplishes this: cfaddne ...

Page 9

Workaround Insure that this kind of sequence of instructions does not occur. Note that adding a small number of intervening instructions may not be sufficient to avoid this problem. If such a sequence must occur, insure that the first and ...

Page 10

Workaround Separating the first and second instruction by one instruction will avoid this error whether or not the coprocessor is operating in serialized or unserialized mode. For example: cfadd32ne c0, c1, c2 nop cfldr64 c3, [r2, #0x0] cfadd32ne c4, c5, ...

Page 11

Note: The effect of branches should also be accounted for the instruction stream as seen by the coprocessor that matters, not the order of instructions in the source code. To avoid this error when entering exception and ...

Page 12

Description 7 The coprocessor can incorrectly update one of its destination accumulators even if the coprocessor instruction should not have been executed or is canceled by the ARM processor. This error can occur if the following is true: 1) The ...

Page 13

Workaround A complete software workaround requires ensuring that data aborts do not occur due to any instruction immediately preceding a coprocessor instruction that writes to an accumulator. The only way to ensure this is to not allow memory operations immediately ...

Page 14

Description 11 An erroneous memory transfer to or from any of the coprocessor general purpose registers c0 through c15 can occur given the following conditions are satisfied: 1) The first instruction two-word load or store - fails ...

Page 15

Description 12 When an operand to the Crunch add/subtract unit is denormalized forced to zero before input to the calculation. The sign is unaffected. This affects the following instructions: - Copies: cfcpys, cfcpyd - Add/Sub: cfadds, cfaddd, cfsubs, ...

Page 16

Revision History Errata Device Document Date Revision Revision E2 Initial Errata March 2005 E2 A April 2007 E2 A April 2007 E2 B April 2007 16 Revision History Functionality Summary of Errata Affected Processor may boot into an invalid state. ...

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