PIC12F635T-I/SN Microchip Technology, PIC12F635T-I/SN Datasheet
PIC12F635T-I/SN
Specifications of PIC12F635T-I/SN
Available stocks
Related parts for PIC12F635T-I/SN
PIC12F635T-I/SN Summary of contents
Page 1
... PIC12F635/PIC16F636/639 *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc. Data Sheet 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41232D ...
Page 2
... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Operating Current kHz, 2.0V, typical - 100 MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical © 2007 Microchip Technology Inc. Peripheral Features: • 6/12 I/O pins with individual direction control: - High-current source/sink for direct LED drive - Interrupt-on-change pin - Individually programmable weak pull-ups/ ...
Page 4
... Analog Front-End section (PIC16F639 only). V SST this document unless otherwise stated. SS DS41232D-page 2 Data Memory I/O EEPROM (bytes) 64 128 6 128 256 12 128 256 12 Low Frequency Comparators Analog Front-End treated DDT DD is treated SST © 2007 Microchip Technology Inc. ...
Page 5
... C1IN+ GP1 6 C1IN- GP2 5 C1OUT (1) GP3 4 — GP4 3 — GP5 2 — — 1 — — 8 — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 GP0/C1IN+/ICSPDAT/ULPWU 2 7 GP1/C1IN-/ICSPCLK 6 3 GP2/T0CKI/INT/C1OUT GP0/CIN+/ICSPDAT/ULPWU 6 GP1/CIN-/ICSPCLK ...
Page 6
... REF Pull-ups Basic Y ICSPDAT/ULPWU Y V /ICSPCLK REF Y — (2) Y MCLR OSC2/CLKOUT Y OSC1/CLKIN — — — — — — — — — — — — — — © 2007 Microchip Technology Inc. ...
Page 7
... RC4 5 C2OUT RC5 4 — — 16 — — 13 — — 14 — — 15 — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 12 RA0/C1IN+/ICSPDAT/ULPWU 1 RA1/C1IN-/ PIC16F636 10 RA2/T0CKI/INT/C1OUT 3 PP RC0/C2IN Timer Interrupts — IOC — IOC ...
Page 8
... REF Y — (2) Y MCLR OSC2/CLKOUT Y OSC1/CLKIN — — — CS — SCLK — CCLK/SDIO — — — — (3) — V DDT (4) — V SST — — — — — — — — — — treated DDT DD is treated SST © 2007 Microchip Technology Inc. ...
Page 9
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 223 DS41232D-page 7 ...
Page 10
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 8 © 2007 Microchip Technology Inc. ...
Page 11
... Oscillator Oscillator T1G T1CKI Timer0 T0CKI Cryptographic Module © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Block Diagrams and pinout descriptions of the devices are as follows: • PIC12F635 (Figure 1-1, Table 1-1) • PIC16F636 (Figure 1-2, Table 1-2) • PIC16F639 (Figure 1-3, Table 1-3) 13 ...
Page 12
... Reset Programmable Low-Voltage Detect Wake-up T1CKI Reset MCLR Timer1 2 Analog Comparators and Reference 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5 PORTC Indirect Addr RC0 RC1 RC2 RC3 RC4 RC5 T1G EEDAT 256 bytes Data EEPROM EEADDR © 2007 Microchip Technology Inc. ...
Page 13
... OSC2/CLKOUT Low-voltage Detect 8 MHz 31 kHz Internal Internal Oscillator Oscillator MCLR V Timer0 T0CKI K Module EELOQ C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 8 Data Bus Program Counter RAM 128 8-level Stack bytes (13-bit) File Registers (1) RAM Addr 9 Addr MUX ...
Page 14
... Timer1 clock. XTAL — XTAL connection. ST — T reference clock. OSC D — Power supply for microcontroller. D — Ground reference for microcontroller. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description D = Direct © 2007 Microchip Technology Inc. ...
Page 15
... RC5 Legend Analog input or output HV = High Voltage TTL = TTL compatible input © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Output Type Type TTL — General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. AN — Comparator 1 input – positive. ...
Page 16
... General purpose I/O. TTL — Digital clock input for SPI communication. — OD Output with internal pull-up resistor for AFE error signal. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Description D = Direct OD = Open Drain © 2007 Microchip Technology Inc. ...
Page 17
... SST Legend Analog input or output HV = High Voltage TTL = TTL compatible input © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Output Type Type TTL CMOS General purpose I/O. — CMOS Digital output representation of analog input signal to LC pins. — Current Received signal strength indicator. Analog current that is proportional to input amplitude. — ...
Page 18
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 16 © 2007 Microchip Technology Inc. ...
Page 19
... Bank 1 is selected 0 1 Bank 2 is selected 1 0 Bank 3 is selected 1 1 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 FIGURE 2-1: PROGRAM MEMORY MAP AND STACK OF THE PIC12F635 PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector ...
Page 20
... The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS41232D-page 18 © 2007 Microchip Technology Inc. ...
Page 21
... Encoder License Agreement” regarding implementation of the module and access to related EE ® registers. The “K L Encoder License Agreement” may be accessed through the Microchip web site EE OQ located at www.microchip.com/K © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 File File Address Address (1) 80h Accesses ...
Page 22
... Accesses 1F0h Bank 0 1FFh Bank 3 © 2007 Microchip Technology Inc. ...
Page 23
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mis- match exists. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 ...
Page 24
... LVDL1 LVDL0 --00 -000 --00 -000 IOCA1 IOCA0 --00 0000 --00 0000 WDA1 WDA0 --11 -111 --11 -111 — — VR1 VR0 0-0- 0000 0-0- 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ---- — — — — © 2007 Microchip Technology Inc. ...
Page 25
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 ...
Page 26
... LVDL1 LVDL0 --00 -000 --00 -000 IOCA1 IOCA0 --00 0000 --00 0000 WDA1 WDA0 --11 -111 --11 -111 — — VR1 VR0 0-0- 0000 0-0- 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ---- — — — — © 2007 Microchip Technology Inc. ...
Page 27
... Encoder License Agreement” regarding implementation of the module and access to related registers. The “K Encoder License Agreement” may be accessed through the Microchip web site located at www.microchip.com contacting your local Microchip Sales Representative. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 5 Bit 4 ...
Page 28
... Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (ADDWF, ADDLW, SUBLW, SUBWF instructions) R/W-x R/W-x R/W-x (1) ( bit Bit is unknown (1) (1) © 2007 Microchip Technology Inc. ...
Page 29
... Microchip Technology Inc. PIC12F635/PIC16F636/639 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”. ...
Page 30
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1,3) (2) INTE RAIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,3) (2) R/W-0 R/W-x INTF RAIF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 31
... Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 ...
Page 32
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1) C2IF C1IF OSFIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 R/W-0 — TMR1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 33
... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> the Configuration Word register for this bit to control the BOR. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-1 R/W-x U-0 (1) SBOREN — ...
Page 34
... Example 2-1. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE family has an INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;INC POINTER FSR,4 ;all done? NEXT ;no clear next ;yes continue © 2007 Microchip Technology Inc. ...
Page 35
... DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639 Direct Addressing From Opcode 6 RP1 RP0 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, see Figure 2-2. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 Indirect Addressing ...
Page 36
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 34 © 2007 Microchip Technology Inc. ...
Page 37
... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
Page 38
... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. DS41232D-page 36 R/W-0 R-1 R-0 (1) IRCF0 OSTS HTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R/W-0 LTS SCS bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 39
... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.4 External Clock Modes 3 ...
Page 40
... DD ® ® and PIC ® Oscillator Design” ® Oscillator CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode © 2007 Microchip Technology Inc. ...
Page 41
... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
Page 42
... Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 43
... Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING ...
Page 44
... HFINTOSC LFINTOSC IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC IRCF <2:0> 0 System Clock DS41232D-page 42 Start-up Time 2-cycle Sync 0 2-cycle Sync 0 0 LFINTOSC turns off unless WDT or FSCM is enabled 0 Running Running Running © 2007 Microchip Technology Inc. ...
Page 45
... Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)” ...
Page 46
... FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC T T OST OSC1 0 1 1022 1023 OSC2 Program Counter System Clock DS41232D-page © 2007 Microchip Technology Inc. ...
Page 47
... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
Page 48
... Detected Test Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 — — RAIF 0000 000x 0000 000x SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu TMR1IE 000- 00-0 000- 00-0 TMR1IF 000- 00-0 000- 00-0 © 2007 Microchip Technology Inc. ...
Page 49
... MOVLW 0Ch ;Set RA<3:2> as inputs MOVWF TRISA ;and set RA<5:4,1:0> ;as outputs © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2 Additional Pin Functions Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/pull-down option. RA0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions ...
Page 50
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R-1 R/W-1 TRISA4 TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x RA1 RA0 bit Bit is unknown R/W-1 R/W-1 TRISA1 TRISA0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 51
... WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled; otherwise, the bit can not be written and reads as ‘1’. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as ‘1’ © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ...
Page 52
... Q2 cycle), then the RAIF interrupt flag may not get set. R/W-0 R/W-0 R/W-0 (2) (2) (3) IOCA4 IOCA3 IOCA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) (1) R/W-0 R/W-0 IOCA1 IOCA0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 53
... Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Application Note AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879). © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 EXAMPLE 4-2: BANKSEL PORTA BSF PORTA,0 MOVLW H’7’ ...
Page 54
... In-Circuit Serial Programming™ data • an analog input for the Ultra Low-Power Wake-up Analog ( Weak RAPU Weak 0 1 Analog (1) Input Mode PORTA RA0/C1IN+/ICSPDAT/ULPWU V DD I/O pin – ULP V SS ULPWUE © 2007 Microchip Technology Inc. ...
Page 55
... Interrupt-on- change RD PORTA To Comparator Note 1: Comparator mode determines Analog Input mode. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2.4.3 Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: • a general purpose I/O • the clock input for Timer0 • ...
Page 56
... Program mode entry FIGURE 4-4: BLOCK DIAGRAM OF RA3 Data Bus RD TRISA RD PORTA WR IOCA RD Interrupt-on- change DS41232D-page 54 MCLRE Program Mode HV Detect MCLRE Reset V SS MCLRE IOCA PORTA WURE Sleep V DD Weak Input pin © 2007 Microchip Technology Inc. ...
Page 57
... T1G To Timer1 Note 1: Oscillator modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 4.2.4.6 Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • ...
Page 58
... TMR1ON 0000 0000 uuuu uuuu CxSYNC ---- --10 ---- --10 CM0 0000 0000 0000 0000 PS0 1111 1111 1111 1111 TRISA0 --11 1111 --11 1111 WPUDA0 --11 -111 --11 -111 IOCA0 --00 0000 --00 0000 WDA0 --11 -111 --11 -111 © 2007 Microchip Technology Inc. ...
Page 59
... Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 EXAMPLE 4-3: INITIALIZING PORTC BANKSEL PORTC CLRF PORTC ...
Page 60
... FIGURE 4-7: BLOCK DIAGRAM OF RC0 AND RC1 Data Bus PORTC TRISC Analog Input Mode RD TRISC RD PORTC To Comparators FIGURE 4-8: BLOCK DIAGRAM OF RC2, RC3 AND RC5 Data Bus PORTC TRISC RD TRISC RD PORTC © 2007 Microchip Technology Inc I/O pin I/O pin V SS ...
Page 61
... RC5 CMCON0 C2OUT C1OUT C2INV TRISC — — TRISC5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 V DD I/O pin V SS Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 ...
Page 62
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 60 © 2007 Microchip Technology Inc. ...
Page 63
... T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter ...
Page 64
... T0CKI input and the Timer0 register is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 15.0 “Electrical Specifications”. © 2007 Microchip Technology Inc. ...
Page 65
... T0CS TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 66
... The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is F /4. When TMR1CS = 1, the clock source is OSC supplied externally. Clock FOSC T1OSCEN Source Mode xxx OSC T1CKI pin x T1LPOSC INTOSCIO DS41232D-page 64 T1CS x 1 © 2007 Microchip Technology Inc. ...
Page 67
... Without CLKOUT T1OSCEN Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 TMR1ON To C2 Comparator Module Timer1 Clock ( ...
Page 68
... Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events. © 2007 Microchip Technology Inc. ...
Page 69
... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 6.9 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output ...
Page 70
... TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. DS41232D-page 68 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /4) R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 71
... Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON T1GINV TMR1GE T1CKPS1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 Bit 2 Bit 1 — — — T1GSS ...
Page 72
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 70 © 2007 Microchip Technology Inc. ...
Page 73
... CINV Note 1: Comparator output is latched on falling edge of Timer1 clock source and Q3 are phases of the four-phase system clock ( held high during Sleep mode. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 comparator is a digital low level. When the analog voltage greater than the analog voltage at ...
Page 74
... D Q Q3*RD CMCON0 EN CL Reset OSC C2SYNC D Q Timer1 (1) clock source CMCON0 D Q Q3*RD CMCON0 EN CL Reset OSC To C1OUT pin To Data Bus Set C1IF bit ). To Timer1 Gate 0 To C2OUT pin 1 To Data Bus Set C2IF bit ). © 2007 Microchip Technology Inc. ...
Page 75
... Source Impedance Analog Voltage Threshold Voltage T © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog ...
Page 76
... CM<2:0> = 111 I/O CIN- COUT I/O CIN+ COUT (pin) I/O Module CIS = Comparator Input Switch (CMCON0<3> Comparator Digital Output COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF (1) Off © 2007 Microchip Technology Inc. ...
Page 77
... C1IN C2IN C2IN+ Legend Analog Input, ports always reads ‘0’ I/O = Normal port I/O Note 1: Reads as ‘0’, unless CxINV = 1. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Two Independent Comparators CM<2:0> = 100 A C1IN- (1) Off A C1IN+ A C2IN- (1) Off A C2IN+ One Independent Comparator CM< ...
Page 78
... CM<2:0> = 001 (Comparator C1 only) • CM<2:0> = 010 (Comparators C1 and C2) In the above modes, both pins remain in Analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch. CxOUT © 2007 Microchip Technology Inc. ...
Page 79
... See the Comparator and Voltage Specifications in Section 15.0 “Electrical Specifications” for more details. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 7.6 Comparator Interrupt Operation The comparator interrupt flag is set whenever there is a change in the output value of the comparator ...
Page 80
... Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. DS41232D-page 78 reset by software © 2007 Microchip Technology Inc. ...
Page 81
... CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O, Comparator output available internally, CV 111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 7.8 Effects of a Reset A device Reset forces the CMCON0 and CMCON1 registers to their Reset states ...
Page 82
... Two comparators with outputs and common reference 111 = Comparators off. CxIN pins are configured as digital I/O DS41232D-page 80 R/W-0 R/W-0 R/W-0 C1INV CIS CM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - R/W-0 R/W-0 CM1 CM0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 83
... See the Comparator Block Diagram (Figure 7-2) and the Timer1 Block Diagram (Figure 6-1) for more information. Note: References to the comparator in this section specifically are Comparator C2 on the PIC16F636/639. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 referring to referring to DS41232D-page 81 ...
Page 84
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) © 2007 Microchip Technology Inc. R/W-1 R/W-0 T1GSS CMSYNC bit Bit is unknown R/W-1 R/W-0 T1GSS C2SYNC bit Bit is unknown ...
Page 85
... DD REF REF The full range cannot be realized due the construction of the module. See Figure 7-10. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 7.11.3 OUTPUT CLAMPED TO V The CV output voltage can be set to Vss with no REF power consumption by configuring VRCON as follows: • VREN = 0 • VRR = 1 • ...
Page 86
... VR<3:0> = 0000 VRR Note 1: Care should be taken to ensure V within the comparator common mode input range. See Section 15.0 “Electrical Specifica- tions” for more detail. R/W-0 R/W-0 VR2 VR1 VR0 bit Bit is unknown . R VRR 8R remains REF © 2007 Microchip Technology Inc. ...
Page 87
... TRISA5 TRISA4 TRISA3 TRISA2 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 VRCON VREN — VRR Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 4 Bit 3 Bit 2 Bit 1 CINV CIS CM2 CM1 — ...
Page 88
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 86 © 2007 Microchip Technology Inc. ...
Page 89
... PLVD OPERATION V DD PLVD Trip Point LVDIF Set by Hardware © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The PLVD module includes the following capabilities: • Eight programmable trip points • Interrupt on falling V • Stable reference indication • Operation during Sleep A Block diagram of the PLVD module is shown in Figure 8-1 ...
Page 90
... LVDIE and PEIE bits are set, the device will wake from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine upon completion of the first instruction after waking from Sleep. © 2007 Microchip Technology Inc. ...
Page 91
... PIR1 OSFIF C2IF C1IF LVDCON — — IRVST Legend unknown unimplemented read as ‘0’. Shaded cells are not used by the PLVD module. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-0 U-0 R/W-1 (1) LVDEN — LVDL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 92
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 90 © 2007 Microchip Technology Inc. ...
Page 93
... EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits Note 1: PIC16F636/639 only. Read as ‘0’ on PIC12F635. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write) ...
Page 94
... EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1). U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 95
... BSF EECON1,WR ;Start the write BSF INTCON,GIE ;Enable INTS © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 9.4 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 9-3) to the desired value to be written. ...
Page 96
... Value on Value on Bit 0 all other POR, BOR Resets RAIF 0000 000x 0000 000x TMR1IF 0000 00-0 0000 00-0 TMR1IE 0000 00-0 0000 00-0 EEDAT0 0000 0000 0000 0000 EEADR0 0000 0000 0000 0000 RD ---- x000 ---- q000 ---- ---- ---- ---- © 2007 Microchip Technology Inc. ...
Page 97
... L Encoder License EE OQ Agreement”. ® The “K L Encoder License Agreement” may accessed through the Microchip web site located at www.microchip.com Further information may obtained by contacting your local Microchip Sales Representative. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 95 ...
Page 98
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 96 © 2007 Microchip Technology Inc. ...
Page 99
... The signal levels from all 3 channels are combined such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 11.2 Modulation Circuit The modulation circuit consists of a modulation transistor (FET), internal tuning capacitors and external LC antenna components ...
Page 100
... The AFE has an internal 32 kHz RC oscillator. The oscillator is used in several timers: • Inactivity timer • Alarm timer • Pulse Width timer • Period timer • AGC settling timer 11.14.1 RC OSCILLATOR The RC oscillator is low power, 32 kHz ± 10% over temperature and voltage variations. © 2007 Microchip Technology Inc. “Configurable ...
Page 101
... MCU can take appropriate actions such as lowering channel sensitivity or disabling channels. If the noise source is ignored, the AFE can return to a lower standby current draw state. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The timer is reset when the: • CS pin is low (any SPI command). ...
Page 102
... Sensitivity Control Z A Modulation Depth To Sensitivity X 32 kHZ Oscillator To Sensitivity Y To Sensitivity Z Command Decoder/Controller Configuration Registers RSSI V V SST DDT ÷ 64 WAKEX ÷ 64 WAKEY WAKEZ ÷ 64 Watchdog B AGC Output Enable Timer Filter SCLK/ALERT CS LFDATA/RSSI/ CCLK/SDIO MCU © 2007 Microchip Technology Inc. ...
Page 103
... FIGURE 11-2: LC INPUT PATH © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 101 ...
Page 104
... DS41232D-page 102 Ant. X Ant. Y Ant Data LED 5 16 RFEN SCLK/ALERT DDT SST 8 13 LCX LCCOM 9 12 LCY LCZ 10 11 ferrite-core ferrite-core coil coil © 2007 Microchip Technology Inc. LED UHF Transmitter PIC16F639 MCU (PIC16F636 Input Analog Front-End Transponder +3V +3V ...
Page 105
... Missing cycles may result in failing the output enable condition. FIGURE 11-5: OUTPUT ENABLE FILTER TIMING T STAB ( AGC PAGC Demodulator Output AFE Wake-up and AGC Stabilization © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ) and OEH . OEH Required Output Enable Sequence T GAP t T OEH AGC Gap Pulse t T ...
Page 106
... High time after T PAGC STAB AGC PAGC DS41232D-page 104 LFDATA Output LF Coil Input T T PAGC GAP Gap (need “high”) Pulse t T OEH t T OET Filter starts AGC Start bit t T OEL Filter is passed and LFDATA is enabled © 2007 Microchip Technology Inc. ...
Page 107
... OEH OET - or T > T OEL OET • A Soft Reset SPI command is received. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 If the filter resets due to a long high (T high-pulse timer will not begin timing again until after a gap of T and another low-to-high transition occurs on E ...
Page 108
... An AGC Preserve Off command is needed to disable the Section 11.32.2.5 “AGC Preserve On Command” and Section 11.32.2.6 Command” for AGC Preserve commands). ), the AGC Input Sensitivity (Typical) 3 and AGC AGC preserve feature (see “AGC Preserve Off © 2007 Microchip Technology Inc. ...
Page 109
... The 75% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 11-3 for minimum modulation depth requirement settings. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 TABLE 11-3: SETTING FOR MINIMUM MODULATION DEPTH ...
Page 110
... Amplitude 0 DS41232D-page 108 Modulation Depth (%) = Coil Input Strength PP Modulation Depth (%) = t Input signal with modulation depth = 30% Demodulated LFDATA Output when MODMIN Setting = 25% (LFDATA output = toggled) t Demodulated LFDATA Output if MODMIN Setting = 50% (LFDATA output = not toggled 100 100% = 30% 10 © 2007 Microchip Technology Inc. ...
Page 111
... Configuration Register 5 1 Configuration Register 6 1 (Column Parity Register) © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 11.25 Error Detection of AFE Configuration Register Data The AFE’s Configuration registers are volatile memory. Therefore, the contents of the registers can be corrupted or cleared by any electrical incidence such as battery disconnect ...
Page 112
... Note: Voltage on L voltage must not exceed the maximum LC input voltage. R LIM D 1 FLAT L POOL Air Coil FLAT R COM DD combined with coil input CCOM LCX LCY LCZ LCCOM C COM voltage when in strong fields. © 2007 Microchip Technology Inc. ...
Page 113
... Carrier Clock. See Configuration Register 1 (Register 11-2) for more details. 11.31.1 DEMODULATOR OUTPUT The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 11-9 for the demodulator output. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ) ...
Page 114
... Configuration Register 0 (Register 11-1). If the criteria is met, the output is available after the low timing (T OEL demodulated output when the Output Enable Filter is enabled. DS41232D-page 112 ) of the Enable Filter. Figure 11-11 and Figure 11-12 shows examples of © 2007 Microchip Technology Inc. ...
Page 115
... FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS) Input Signal FIGURE 11-12: NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS) Input Signal © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 LFDATA Output No LFDATA Output DS41232D-page 113 ...
Page 116
... Carrier Clock Output 0 0: RSSI Output 1 1: RSSI Output 1 • Configuration Register 2 (Register 11-3), CLKDIV<7>: 0: Carrier Clock/1 1: Carrier Clock/4 • Configuration Register 0 (Register 11-1): all bits are affected • Configuration Register 5 (Register 11-6) DS41232D-page 114 ) is AGC © 2007 Microchip Technology Inc. ...
Page 117
... FIGURE 11-13: CARRIER CLOCK OUTPUT EXAMPLES (A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION Carrier Clock Output Carrier Input (B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION Carrier Clock Output Carrier Input © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 115 ...
Page 118
... Configuration Register 0 (Register 11-1): all bits are affected. DS41232D-page 116 FIGURE 11-14: RSSI OUTPUT PATH RSSI Output Current Generator Current Output V DD Off if RSSI active RC3/LFDATA/RSSI/CCLK Pin RSSIFET RSSI Pull-down MOSFET (controlled by Config. 2, bit 8) © 2007 Microchip Technology Inc. ...
Page 119
... FIGURE 11-15: RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Input Voltage ( DS41232D-page 117 ...
Page 120
... Pin is a digital output (LFDATA) so long high. During SPI communication, the pin is the SPI data input (SDI) unless performing a register Read, where it will be the SPI data output (SDO). ALERT (open collector output) LFDATA (output) Figure 11-15, © 2007 Microchip Technology Inc. ...
Page 121
... Clock in 16-bit SPI Write sequence - command, address, data and parity bit. • Command, address, data and parity bit. 5. Change LFDATA/RSSI/CCLK/SDIO connected pin to input. 6. Raise CS to complete the SPI Write. 7. Change SCLK/ALERT back to input. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 16 Clocks for Write Command, Address and Data 1/F ...
Page 122
... Next eight bits are the Configuration register data. • The last bit is the Configuration register row parity bit. 9. Raise CS to complete the SPI Read. 10. Change SCLK/ALERT back to input. . CSH T CSH Clocks for Read Result CSSC CS ALERT (output LFDATA (output) © 2007 Microchip Technology Inc. ...
Page 123
... Not Used 0111 Note: ‘P’ denotes the row parity bit (odd parity) for the respective data byte. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19). SDI data is loaded into the AFE on the rising edge of SCLK and SDO data is clocked out on the falling edge of SCLK ...
Page 124
... SPI, except STATUS register, which is readable only. Bit 0 of each register is a row parity bit (except for the AFE Status Register 7) that makes the register contents an odd number LSb Row Parity Bit © 2007 Microchip Technology Inc. ...
Page 125
... LCYEN: LCY Enable bit 1 = Disabled 0 = Enabled bit 1 LCXEN: LCX Enable bit 1 = Disabled 0 = Enabled bit 0 R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Bit 7 Bit 6 Bit 5 Bit 4 OEH OEL ALRTIND ...
Page 126
... Bit is cleared R/W-0 R/W-0 R/W-0 LCYTUN4 LCYTUN3 LCYTUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 LCXTUN1 LCXTUN0 R1PAR bit Bit is unknown R/W-0 R/W-0 R/W-0 LCYTUN1 LCYTUN0 R2PAR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 127
... R4PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits Note 1: Assured monotonic increment (or decrement) by design. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R/W-0 R/W-0 R/W-0 LCZTUN4 LCZTUN3 LCZTUN2 U = Unimplemented bit, read as ‘ ...
Page 128
... R/W-0 R/W-0 COLPAR4 COLPAR3 COLPAR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 LCZSEN1 LCZSEN0 R5PAR bit Bit is unknown ; or otherwise, blocks the STAB R/W-0 R/W-0 R/W-0 COLPAR1 COLPAR0 R6PAR bit 0 © 2007 Microchip Technology Inc. ...
Page 129
... Soft Reset Executed 0 Legend unchanged Note 1: See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft Reset execution. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 R-0 R-0 R-0 AGCACT WAKEZ WAKEY U = Unimplemented bit, read as ‘0’ ...
Page 130
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 128 © 2007 Microchip Technology Inc. ...
Page 131
... The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1). © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 12.1 Configuration Bits The Configuration Word bits can be programmed (read as ‘ ...
Page 132
... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41232D-page 130 WURE FCMEN IESO PWRTE WDTE FOSC2 P = Programmable’ ‘0’ = Bit is cleared (1) (2) (4) DD BOREN1 BOREN0 bit 8 FOSC1 FOSC0 bit Unimplemented bit, read as ‘0’ Bit is unknown © 2007 Microchip Technology Inc. ...
Page 133
... PWRT 11-bit Ripple Counter LFINTOSC Note 1: Refer to the Configuration Word register (Register 12-1). © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-3 ...
Page 134
... MCLR is internally tied to V weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option. to rise to an acceptable level for details (Section 15.0 at the MCLR SS should be used when SS and an internal DD © 2007 Microchip Technology Inc. . ...
Page 135
... FIGURE 12-2: RECOMMENDED MCLR CIRCUIT V DD PIC12F635/PIC16F636/639 greater) MCLR C1 0.1 F (optional, not critical) © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 DS41232D-page 133 ...
Page 136
... Brown-out Reset and the Power-up Timer will be re-initialized. Once V rises above V BOD 64 ms Reset. for less than ( & rises DD while the Power-up Timer is BOD DD , the Power-up Timer will execute a V BOD V BOD V BOD © 2007 Microchip Technology Inc. ...
Page 137
... Legend unchanged unknown © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 12.8 Power Control (PCON) Register The Power Control register, PCON (address 8Eh), has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred ...
Page 138
... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS41232D-page 136 T PWRT T OST T PWRT T OST DD T PWRT T OST © 2007 Microchip Technology Inc. ) ...
Page 139
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 MCLR Reset WDT Reset (1) Brown-out Reset Wake-up Reset ...
Page 140
... Program Status Counter Register 000h 0001 1xxx 000h 000u uuuu 000h 0001 0uuu 000h 0000 uuuu uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu 000h 0001 1xxx © 2007 Microchip Technology Inc. PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu --01 --0x ...
Page 141
... The GIE is cleared to disable any further interrupt. • The return address is pushed onto the stack. • The PC is loaded with 0004h. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles ...
Page 142
... If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set. Wake-up (If in Sleep mode) T0IF T0IE INTF INTE RAIF RAIE PEIE GIE © 2007 Microchip Technology Inc. The interrupt can be Interrupt to CPU ...
Page 143
... IOCA5 PIR1 EEIF LVDIF CRIF PIE1 EEIE LVDIE CRIE Legend unknown unchanged, – = unimplemented, read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. Note 1: PIC16F636/639 only. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 (1) (2) Interrupt Latency ...
Page 144
... W_TEMP,W ;Swap W_TEMP into W DS41232D-page 142 Note: The PIC12F635/PIC16F636/639 normally does not require saving the PCLATH. However, if computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR. © 2007 Microchip Technology Inc. ...
Page 145
... CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, HFINTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT ...
Page 146
... WSTPS1 WDTPS0 SWDTEN T0SE PSA PS2 PS1 PWRTE WDTE FOSC2 FOSC1 R/W-0 R/W-0 (1) WDTPS0 SWDTEN bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets ---0 1000 ---0 1000 PS0 1111 1111 1111 1111 FOSC0 — — © 2007 Microchip Technology Inc. ...
Page 147
... Comparator output changes state. 5. Interrupt-on-change. 6. External Interrupt from INT pin. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction ( prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 148
... These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. (3) 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) © 2007 Microchip Technology Inc. ...
Page 149
... To Normal Connections *Isolation devices (as required). © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 12.16 In-Circuit Debugger Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB a 14-pin device is not practical. A special 20-pin PIC16F636 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user ...
Page 150
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 148 © 2007 Microchip Technology Inc. ...
Page 151
... PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 TABLE 13-1: OPCODE FIELD DESCRIPTIONS ...
Page 152
... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2007 Microchip Technology Inc. ...
Page 153
... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 BCF Syntax: k Operands: Operation: Status Affected: ...
Page 154
... Decrement f [ label ] DECF f 127 d [0,1] ( (destination) Z Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. ...
Page 155
... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: ...
Page 156
... Words: Cycles: Example: Move label ] MOVWF 127 (W) (f) None Move data from W register to register ‘f’ MOVW OPTION F Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP © 2007 Microchip Technology Inc. ...
Page 157
... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 RETLW Return with literal in W Syntax: [ label ] Operands Operation: k (W); TOS Status Affected: None Description: The W register is loaded with the eight-bit literal ‘ ...
Page 158
... The processor is put into Sleep mode with the oscillator stopped. Subtract W from literal [ label ] SUBLW 255 k - (W) W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register W<3:0> k<3:0> W<3:0> k<3:0> © 2007 Microchip Technology Inc. ...
Page 159
... Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 XORLW Syntax: Operands: Operation: Status Affected: Description: f< ...
Page 160
... PIC12F635/PIC16F636/639 NOTES: DS41232D-page 158 © 2007 Microchip Technology Inc. ...
Page 161
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 162
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 163
... Microchip Technology Inc. PIC12F635/PIC16F636/639 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 164
... SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. © 2007 Microchip Technology Inc. ® ...
Page 165
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 should be used when applying a ‘low’ level to the MCLR pin, rather than pulling this pin directly to V © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ........................................................................... -0. >V ...
Page 166
... PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40°C T 5.5 5.0 4.5 4.0 3.6 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Cross-hatched area is for HFINTOSC and EC modes only. DS41232D-page 164 Frequency (MHz Frequency (MHz) T +125°C A +85°C © 2007 Microchip Technology Inc. ...
Page 167
... FIGURE 15-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 -40 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 ± 5% ± 2% ± 1% 3.0 3.5 4.0 4.5 V (V) DD AND TEMPERATURE DD 5.0 5.5 DS41232D-page 165 ...
Page 168
... V/ms See Section 12.3 “Power-on Reset” for details. 2.0 2.1 2.2 V can be lowered in Sleep mode without losing RAM data. T +85°C for industrial A T +125°C for extended A Conditions < MHz < MHz, HFINTOSC, EC < MHz < MHz © 2007 Microchip Technology Inc. ...
Page 169
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature Min Typ† ...
Page 170
... PLVD Current A 3.0 A 5.0 (3) A 2.0 Comparator Current A 3.0 A 5.0 (1) A 2.0 CV Current REF (high-range) A 3.0 A 5.0 (1) A 2.0 CV Current REF (low-range) A 3.0 A 5.0 (3) A 2.0 T1OSC Current A 3.0 A 5.0 ; WDT disabled. MCU only, Analog © 2007 Microchip Technology Inc. ...
Page 171
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature ...
Page 172
... WDT Current 3.0 5.0 (1) 3.0 BOR Current 5.0 2.0 PLVD Current 3.0 5.0 (1) 2.0 Comparator Current 3.0 5.0 (1) 2.0 CV Current REF (high-range) 3.0 5.0 (1) 2.0 CV Current REF (low-range) 3.0 5.0 (3) 2.0 T1OSC Current 3.0 5 current from this © 2007 Microchip Technology Inc. ...
Page 173
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 “Using the Data EEPROM” for additional information. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 174
... E/W +85°C T +125° Using EECON1 to read/write V = Minimum operating MIN voltage ms Year Provided no other specifications are violated E/W - +85°C A E/W - +85°C A E/W +85°C T +125° Minimum operating MIN voltage V ms Year Provided no other specifications are violated © 2007 Microchip Technology Inc. ...
Page 175
... Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which V DD © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Min Typ† Max Units 2.0 — ...
Page 176
... Comparator Current A 3.0 (1) A 2.0 CV Current REF (high-range) A 3.0 (1) A 2.0 CV Current REF (low-range) A 3.0 (1) A 2.0 T1OSC Current A 3 Input = Continuous DD Wave (CW); A 3.6 Amplitude = 300 3.6 All channels enabled ALERT = 3.6 A 3.6 A 3 ALERT = © 2007 Microchip Technology Inc. ...
Page 177
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 “Using the Data EEPROM” for additional information © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 178
... OSC1 - +85°C A +85°C T +125°C A Using EECON1 to read/write V = Minimum operating voltage MIN Provided no other specifications are violated - +85° +85°C A +85°C T +125° Minimum operating voltage MIN Provided no other specifications are violated © 2007 Microchip Technology Inc. ...
Page 179
... Ambient Temperature Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (P © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 +125°C Typ Units 84.6 °C/W 8-pin PDIP package 163.0 °C/W 8-pin SOIC package PIC12F635 52 ...
Page 180
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 15-4: LOAD CONDITIONS Load Condition Pin Legend for all pins for OSC2 output DS41232D-page 178 T Time osc OSC1 SCLK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance L © 2007 Microchip Technology Inc. ...
Page 181
... All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Q1 ...
Page 182
... MHz V = 3.5V, 25°C DD MHz 2.5V V 5.5V, DD 0°C T +85°C A MHz 2.0V V 5.5V, DD -40°C T +85°C (Ind.), A -40°C T +125°C (Ext kHz 2.0V, -40°C to +85° 3.0V, -40°C to +85° 5.0V, -40°C to +85°C DD © 2007 Microchip Technology Inc. ...
Page 183
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Fetch Read Q1 Q2 OS11 OS20 ...
Page 184
... Asserted low. FIGURE 15-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41232D-page 182 BOR 37 33 HYST (Device not in Brown-out Reset) © 2007 Microchip Technology Inc. ...
Page 185
... OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 F and 0.01 F values in parallel are recommended. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 +125°C Min Typ† Max Units 2 — — ...
Page 186
... N = prescale value (2, 4, ..., 256) — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value ( — — ns 32.768 — kHz — — Timers in Sync OSC mode © 2007 Microchip Technology Inc. ...
Page 187
... PLVDS * These parameters are characterized but not tested † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 +125°C Min Typ† — ...
Page 188
... Operating Voltage V Range 2.0V-5.5V DD Min Typ† Max Units 1.900 2.0 2.100 2.000 2.1 2.200 2.100 2.2 2.300 2.200 2.3 2.400 3.825 4.0 4.175 4.025 4.2 4.375 4.325 4.5 4.675 — 50 — 25 +85°C Conditions 5. 3.0V DD © 2007 Microchip Technology Inc. ...
Page 189
... Required output enable filter high time must account for input path analog delays (= T 2: Required output enable filter low time must account for input path analog delays (= T © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2 ...
Page 190
... Viewed from the pin input: clock (Note 2) 32 (~1ms) — — count 32 (~1ms) — — 64 (~2ms) — — 128 (~4ms) — — OEH OEL DR +85°C for industrial PP Conditions 3.0V 3.0V ) OSC E . PRES OSC OSC = 125 kHz OSC OSC + © 2007 Microchip Technology Inc. ...
Page 191
... Required output enable filter high time must account for input path analog delays (= T 2: Required output enable filter low time must account for input path analog delays (= T © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2 ...
Page 192
... SCLK edge when CS is high — 10 — 90% of amplitude — 10 — 10% of amplitude 3.6V +85°C for industrial PP Conditions 3.0V. Time is measured from 10% 3.0V. Time is measured from 90% © 2007 Microchip Technology Inc. ...
Page 193
... Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC 5.5V 5 ...
Page 194
... EC Mode 6 MHz 8 MHz 10 MHz 12 MHz F OSC vs. F OVER V (HS MODE) OSC DD Typical IDD vs FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz 5.5V 5.0V 4.5V 20 MHz © 2007 Microchip Technology Inc. ...
Page 195
... Typical: Statistical Mean @25°C 800 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 700 600 500 400 300 200 100 0 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. F OVER V (HS MODE) OSC DD Maximum IDD vs FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz ...
Page 196
... DS41232D-page 194 vs. V OVER F (XT MODE) DD OSC XT Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD vs. V OVER F (EXTRC MODE) DD OSC EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 197
... V OVER Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst Case Temp (-40°C to 125° 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. V OVER F (EXTRC MODE) DD OSC EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ ...
Page 198
... DS41232D-page 196 (LP MODE) OSC LP Mode 32 kHz Maximum 32 kHz Typical 3.0 3.5 4.0 V (V) DD vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC 4.5 5.0 5.5 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz © 2007 Microchip Technology Inc. ...
Page 199
... Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 © 2007 Microchip Technology Inc. PIC12F635/PIC16F636/639 vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) ...
Page 200
... MODE, ALL PERIPHERALS DISABLED) DD Maximum (Sleep Mode all Peripherals Disabled) Max. 125°C Max. 85°C 3.0 3.5 4.0 V (V) DD vs. V (BOTH COMPARATORS ENABLED Maximum Typical 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 4.5 5.0 5.5 © 2007 Microchip Technology Inc. ...