PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet
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... Microcontrollers with LCD Driver 2010 Microchip Technology Inc. PIC18F85J90 Family Data Sheet 64/80-Pin, High-Performance and nanoWatt Technology DS39770C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Two Pins • In-Circuit Debug with 3 Breakpoints via Two Pins • Operating Voltage Range: 2.0V to 3.6V • On-Chip 2.5V Regulator Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F63J90 8K 4096 PIC18F64J90 16K 8192 PIC18F65J90 32K 16384 PIC18F83J90 8K 4096 PIC18F84J90 16K 8192 PIC18F85J90 ...
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... DDCORE CAP RF7/AN5/SS/SEG25 11 RF6/AN11/SEG24 12 RF5/AN10/CV /SEG23 REF 13 RF4/AN9/SEG22 14 RF3/AN8/SEG21 15 RF2/AN7/C1OUT/SEG20 16 Note 1: The CCP2 pin placement depends on the CCP2MX bit setting. DS39770C-page PIC18F63J90 PIC18F64J90 PIC18F65J90 Pins are up to 5.5V tolerant 50 49 RB0/INT0/SEG30 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9 46 45 RB3/INT3/SEG10 RB4/KBI0/SEG11 44 RB5/KBI1/SEG29 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 ...
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... CAP RF7/AN5/SS/SEG25 13 RF6/AN11/SEG24 14 RF5/AN10/CV /SEG23 15 REF RF4/AN9/SEG22 16 RF3/AN8/SEG21 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: The CCP2 pin placement depends on the CCP2MX bit setting. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY PIC18F83J90 PIC18F84J90 PIC18F85J90 Pins are up to 5.5V tolerant RJ2/SEG34 59 RJ3/SEG35 58 RB0/INT0/SEG30 57 RB1/INT1/SEG8 56 RB2/INT2/SEG9 ...
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... Packaging Information.............................................................................................................................................................. 393 Appendix A: Revision History............................................................................................................................................................. 399 Appendix B: Migration Between High-End Device Families............................................................................................................... 400 Index .................................................................................................................................................................................................. 403 The Microchip Web Site ..................................................................................................................................................................... 413 Customer Change Notification Service .............................................................................................................................................. 413 Customer Support .............................................................................................................................................................................. 413 Reader Response .............................................................................................................................................................................. 414 Product Identification System............................................................................................................................................................. 415 DS39770C-page 6 2010 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY DS39770C-page 7 ...
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... PIC18F85J90 FAMILY NOTES: DS39770C-page 8 2010 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F63J90 • PIC18F83J90 • PIC18F64J90 • PIC18F84J90 • PIC18F65J90 • PIC18F85J90 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with a versatile on-chip LCD driver, while maintaining an extremely competitive price point ...
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... SEGs x 4 COMs) can be driven by 80-pin devices. All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. 2010 Microchip Technology Inc. bytes for ...
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... I/O Ports LCD Driver (available pixels to drive) Timers Capture/Compare/PWM Modules Serial Communications 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2010 Microchip Technology Inc. PIC18F85J90 FAMILY PIC18F63J90 PIC18F64J90 DC – 40 MHz 8K 16K 4096 8192 1024 1024 27 Ports 132 (33 SEGs x 4 COMs) 4 ...
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... Reset ALU<8> Timer (3) LVD MCLR SS ADC Timer2 Timer3 10-Bit MSSP AUSART EUSART PORTA (1,2) RA0:RA7 12 PORTB (1) RB0:RB7 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PORTE PRODL RE0:RE1, (1) RE3:RE7 PORTF 8 (1) RF1:RF7 8 PORTG (1) RG0:RG4 Comparators LCD Driver 2010 Microchip Technology Inc. ...
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... RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more information. 3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Data Bus<8> Data Latch ...
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... SEG14 output for LCD. I/O TTL Digital I/O. I Analog Analog Input 4. O Analog SEG15 output for LCD. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... SEG27 output for LCD. I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX1/CK1). O Analog SEG28 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C™ mode 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... COM2 output for LCD. I/O ST Digital I/O. O Analog COM3 output for LCD. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM2 output. O Analog SEG31 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. O Analog SEG5 output for LCD. I/O ST Digital I/O. O Analog SEG6 output for LCD. I/O ST Digital I/O. O Analog SEG7 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... Analog SEG24 output for LCD. I/O ST Digital I/O. O Analog Analog Input 5. I TTL SPI slave select input. O Analog SEG25 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. O Analog SEG41 output for LCD. I/O ST Digital I/O. O Analog SEG42 output for LCD. I/O ST Digital I/O. O Analog SEG43 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD 2010 Microchip Technology Inc. ...
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... I C™ C/SMBus Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F85J90 FAMILY NOTES: DS39770C-page 30 2010 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXJXX JP C1 and V specifications are met and V specifications are met. IL 2010 Microchip Technology Inc. ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... MHz Source (INTOSC) INTRC Source 31 kHz (INTRC) 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Five of these are selected by the user by programming the FOSC<2:0> Configuration bits. The sixth mode (INTRC) may be invoked under software control; it can also be configured as the default mode on device Resets ...
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... Phase Locked Loop (PLL) in Internal Oscillator modes (see Section 3.4.3 “PLL Frequency Multiplier”). (1) R/W-0 R (2) (2) IRCF0 OSTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (3) (1) (4) R-0 R/W-0 R/W-0 (4) (4) IOFS SCS1 SCS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Section 3.4 “External Oscillator Modes”. The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-0 R/W-0 ...
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... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed Modes”. block is selected whenever 2010 Microchip Technology Inc. ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 3-2 for additional information. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq ...
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... It also allows additional flexibil- ity for controlling the application’s clock speed in software. FIGURE 3-5: PLL BLOCK DIAGRAM HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC2 Phase Comparator OSC1 Mode F OUT Loop Filter 4 VCO 2010 Microchip Technology Inc. SYSCLK ...
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... The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC or vice versa. The frequency of INTRC is not affected by OSCTUNE. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 3.5.3 INTOSC FREQUENCY DRIFT The INTOSC frequency may drift as V ture changes, and can affect the controller operation in a variety of ways ...
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... Table 26-11), following POR, while the controller becomes ready to execute instructions. OSC1 Pin At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level I/O pin, RA7, direction controlled by TRISA<7> consumption are listed in (parameter 38, CSD OSC2 Pin 2010 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC<2:0> ...
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... SEC_RUN mode is entered by setting the SCS<1:0> bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscilla- tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. 2010 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F85J90 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2) ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale 2010 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD 2010 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F85J90 FAMILY NOTES: DS39770C-page 50 2010 Microchip Technology Inc. ...
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... INTRC 11-Bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1) ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39770C-page 52 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises to the point where DD regulator output is sufficient, the Power-up Timer will execute the additional time delay. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY FIGURE 5- ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 5-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel PWRT T PWRT 2010 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 DD ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F85J90 FAMILY T PWRT , V RISE > 3. PWRT ): CASE ...
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... DS39770C-page 56 Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( STKPTR Register POR BOR STKFUL STKUNF 2010 Microchip Technology Inc. ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY MCLR Resets WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt ---- uuuu uuuu uuuu ---- uuuu N/A N/A N/A N/A N/A ---- uuuu ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY MCLR Resets WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt -uuu -uu- (3) -uuu -00- -uuu -00- uu-- uuu- (3) uu-- uuu- uu-- uuu- -uuu u-uu ...
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... See Table 5-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY MCLR Resets WDT Reset ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Section 23.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION WORD FOR PIC18F85J90 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F63J90 8 1FF8h to 1FFFh PIC18F83J90 PIC18F64J90 16 3FF8h to 3FFFh PIC18F84J90 PIC18F65J90 32 7FF8h to 7FFFh PIC18F85J90 2010 Microchip Technology Inc. through Word Addresses ...
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... TOSH TOSL 00h 1Ah 34h 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 2010 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. 2010 Microchip Technology Inc. ...
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... Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh 2010 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Data Memory 000h ...
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... LATC F6Bh LCDDATA5 LATB F6Ah CCPR1H LATA F69h CCPR1L (3) PORTJ F68h CCP1CON (3) PORTH F67h CCPR2H PORTG F66h CCPR2L PORTF F65h CCP2CON PORTE F64h SPBRG2 PORTD F63h RCREG2 PORTC F62h TXREG2 PORTB F61h TXSTA2 PORTA F60h RCSTA2 2010 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY ...
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... SE09 SE08 59, 166 0000 0000 CVR1 CVR0 59, 287 0000 0000 CM1 CM0 59, 281 0000 0111 59, 151 xxxx xxxx 59, 151 xxxx xxxx TMR3CS TMR3ON 59, 149 0000 0000 2 C™ Slave mode. See Section 17.4.3.2 “Address 2010 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY ...
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... CCP2M1 CCP2M0 62, 153 --00 0000 62, 260 0000 0000 62, 265 0000 0000 62, 263 0000 0000 TRMT TX9D 62, 258 0000 -010 OERR RX9D 62, 259 0000 000x 2 C™ Slave mode. See Section 17.4.3.2 “Address 2010 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY register then reads back as ‘000u u1uu’ recom- ...
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... EXAMPLE 6-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue 2010 Microchip Technology Inc. Stack Pointer ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”. 2010 Microchip Technology Inc. ...
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... Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 6.6.2 INSTRUCTIONS AFFECTED BY ...
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... FSR2H F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h Bank 1 001001da through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory 2010 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F85J90 FAMILY NOTES: DS39770C-page 86 2010 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Table Latch (8-bit) TABLAT 2010 Microchip Technology Inc. ...
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... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-x R/W-0 FREE ...
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... Figure 7-3 describes the relevant boundaries of the TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> TBLPTRL 0 2010 Microchip Technology Inc. ...
Page 91
... TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT ...
Page 92
... The CPU will stall for the duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts 2010 Microchip Technology Inc. ...
Page 93
... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
Page 94
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block 2010 Microchip Technology Inc. ...
Page 95
... EECON2 EEPROM Control Register 2 (not a physical register) EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 7.6 Flash Program Operation During Code Protection See Section 23.6 “Program Verification and Code Protection” ...
Page 96
... PIC18F85J90 FAMILY NOTES: DS39770C-page 96 2010 Microchip Technology Inc. ...
Page 97
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F85J90 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 98
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H 2010 Microchip Technology Inc. ...
Page 99
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 100
... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP 2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 101
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 102
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39770C-page 102 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 103
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 ...
Page 104
... R-0 R/W-0 U-0 TX1IF SSPIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 105
... The device voltage is above the regulator’s low-voltage trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J90 FAMILY U-0 R/W-0 R/W-0 — BCLIF LVDIF U = Unimplemented bit, read as ‘ ...
Page 106
... No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 Unimplemented: Read as ‘0’ DS39770C-page 106 R-0 U-0 R/W-0 TX2IF — CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 CCP1IF — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 107
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-0 U-0 TX1IE SSPIE — ...
Page 108
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ DS39770C-page 108 U-0 R/W-0 R/W-0 — BCLIE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. R/W-0 U-0 TMR3IE — bit Bit is unknown ...
Page 109
... CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R-0 U-0 R/W-0 TX2IE — CCP2IE U = Unimplemented bit, read as ‘0’ ...
Page 110
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39770C-page 110 R/W-1 R/W-1 U-0 TX1IP SSPIP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 111
... LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F85J90 FAMILY U-0 R/W-1 R/W-1 — BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 112
... CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ DS39770C-page 112 R-1 U-0 R/W-1 TX2IP — CCP2IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 U-0 CCP1IP — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 113
... For details of bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 114
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS 2010 Microchip Technology Inc. ...
Page 115
... PORT Note 1: I/O pins have diode protection 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 116
... ADCON1 ; for digital inputs MOVLW 0BFh MOVWF TRISA 5V and OSC1/CLKI/RA7 normally INITIALIZING PORTA ; Initialize PORTA by ; clearing output latches ; Alternate method to ; clear output data latches ; Configure A/D ; Value used to initialize ; data direction ; Set RA<7, 5:0> as inputs, ; RA<6> as output 2010 Microchip Technology Inc. ...
Page 117
... Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O ...
Page 118
... Polling of PORTB is not recommended while using the interrupt-on-change feature. RB<5:0> are also multiplexed with LCD segment drives, controlled by bits in the LCDSE1 and LCDSE3 registers. I/O port functionality is only available when the LCD segments are disabled. 2010 Microchip Technology Inc. device from delay. CY ...
Page 119
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O ...
Page 120
... INTEDG2 INTEDG3 TMR0IP INT3IE INT2IE INT1IE INT3IF SE13 SE12 SE11 SE10 SE29 SE28 SE27 SE26 Reset Bit 1 Bit 0 Values on page RB1 RB0 61 LATB1 LATB0 60 TRISB1 TRISB0 60 INT0IF RBIF 57 INT3IP RBIP 57 INT2IF INT1IF 57 SE09 SE08 59 SE25 SE24 59 2010 Microchip Technology Inc. ...
Page 121
... TRIS bit settings. Note: These pins are configured as digital inputs on any device Reset. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. RC< ...
Page 122
... Asynchronous serial receive data input (EUSART module). DIG Synchronous serial data output (EUSART module); takes priority over port data. ST Synchronous serial data input (EUSART module); user must configure as an input. ANA LCD Segment 28 output; disables all other pin functions. 2010 Microchip Technology Inc. ...
Page 123
... SE23 SE22 LCDSE3 SE31 SE30 (1) (1) LCDSE4 SE39 SE38 Legend: Shaded cells are not used by PORTC. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 ...
Page 124
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2010 Microchip Technology Inc. ...
Page 125
... TRISD TRISD7 TRISD6 PORTG RDPU REPU LCDSE0 SE7 SE6 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD<0> data input. O ANA LCD Segment 0 output ...
Page 126
... MOVLW 03h MOVWF TRISE for I/O RE6 None parts has the function of INITIALIZING PORTE ; Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE<1:0> as inputs ; RE<7:2> as outputs 2010 Microchip Technology Inc. ...
Page 127
... TRISG SPIOD CCP2OD CCP1OD LCDCON LCDEN SLPEN LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type O DIG LATE<0> data output PORTE<0> data input. I ANA LCD module bias voltage input ...
Page 128
... MOVLW 07h ; MOVWF CMCON ; Turn off comparators MOVLW 0Fh ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs 2010 Microchip Technology Inc. ...
Page 129
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O ...
Page 130
... C1INV CIS CM2 CVRR CVRSS CVR3 CVR2 SE21 SE20 SE19 SE18 SE29 SE28 SE27 SE26 Reset Bit 1 Bit 0 Values on page RF1 — 60 LATF1 — 60 TRISF1 — 60 PCFG1 PCFG0 59 CM1 CM0 59 CVR1 CVR0 59 SE17 SE16 59 SE25 SE24 59 2010 Microchip Technology Inc. ...
Page 131
... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Although the port itself is only five bits wide, the PORTG<7:5> bits are still implemented to control the weak pull-ups on the I/O ports associated with PORTD, PORTE and PORTJ ...
Page 132
... LCD Segment 26 output; disables all other pin functions. Bit 5 Bit 4 Bit 3 Bit 2 (1) RJPU RG4 RG3 RG2 — LATG4 LATG3 LATG2 TRISG3 TRISG2 SE29 SE28 SE27 SE26 Description Reset Bit 1 Bit 0 Values on page RG1 RG0 60 LATG1 LATG0 60 TRISG1 TRISG0 60 SE25 SE24 59 2010 Microchip Technology Inc. ...
Page 133
... All PORTH pins are multiplexed with LCD segment drives controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY EXAMPLE 10-8: INITIALIZING PORTH CLRF PORTH ...
Page 134
... LCD Segment 43 output; disables all other pin functions. Bit 5 Bit 4 Bit 3 Bit 2 RH5 RH4 RH3 RH2 LATH5 LATH4 LATH3 LATH2 TRISH5 TRISH4 TRISH3 TRISH2 SE45 SE44 SE43 SE42 Description Reset Bit 1 Bit 0 Values on page RH1 RH0 60 LATH1 LATH0 60 TRISH1 TRISH0 60 SE41 SE40 59 2010 Microchip Technology Inc. ...
Page 135
... LCDSE4 register. I/O port functions are only available on these pins when the segments are disabled. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Each of the PORTJ pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up ...
Page 136
... Bit 2 RJ5 RJ4 RJ3 RJ2 LATJ5 LATJ4 LATJ3 LATJ2 TRISJ5 TRISJ4 TRISJ3 TRISJ2 (1) RG4 RG3 RG2 SE37 SE36 SE35 SE34 Description Reset Bit 1 Bit 0 Values on page RJ1 RJ0 60 LATJ1 LATJ0 60 TRISJ1 TRISJ0 60 RG1 RG0 60 SE33 SE32 59 2010 Microchip Technology Inc. ...
Page 137
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 138
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 139
... RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 11.3.1 ...
Page 140
... PIC18F85J90 FAMILY NOTES: DS39770C-page 140 2010 Microchip Technology Inc. ...
Page 141
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 142
... Special Event Trigger) 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 143
... TIMER1 LP OSCILLATOR C1 PIC18F85J90 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER1 (2,3,4) OSCILLATOR Oscillator Freq. C1 Type ( ...
Page 144
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 2010 Microchip Technology Inc. ...
Page 145
... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 146
... PIC18F85J90 FAMILY NOTES: DS39770C-page 146 2010 Microchip Technology Inc. ...
Page 147
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 148
... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSPIF TX1IE SSPIE TX1IP SSPIP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 — TMR2IF TMR1IF 60 — TMR2IE TMR1IE 60 — TMR2IP TMR1IP 2010 Microchip Technology Inc. ...
Page 149
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2010 Microchip Technology Inc. PIC18F85J90 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 150
... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 8 TMR3H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 151
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 152
... PIC18F85J90 FAMILY NOTES: DS39770C-page 152 2010 Microchip Technology Inc. ...
Page 153
... PWM mode Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCP1 match. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register ...
Page 154
... TMR1 TMR3 CCP1 CCP2 TMR2 Timer3 is used for all Capture and Compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. 2010 Microchip Technology Inc. ...
Page 155
... Capture PWM None Compare PWM None PWM Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Interaction DS39770C-page 155 ...
Page 156
... CAPTURE PRESCALERS ; Turn CCP module off ; new prescaler mode ; value and CCP ON ; Load CCP2CON with ; this value TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L 2010 Microchip Technology Inc. ...
Page 157
... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 15.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M<3:0> = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP2IE bit is set. ...
Page 158
... CCP2M2 CCP2M1 CCP2M0 Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 57 PD POR BOR 58 CCP1IF — 60 CCP1IE — 60 CCP1IP — 60 TMR3IF — 60 TMR3IE — 60 TMR3IP — 60 TRISC1 TRISC0 60 — TRISE1 TRISE0 60 TRISG1 TRISG0 TMR1CS TMR1ON TMR3CS TMR3ON 2010 Microchip Technology Inc. ...
Page 159
... The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY A PWM output (Figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
Page 160
... PWM period, the CCP2 pin will not be cleared. 9.77 kHz 39.06 kHz FFh FFh OSC log --------------- F PWM = -----------------------------bits 2 log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 2010 Microchip Technology Inc. ...
Page 161
... CCPR2H Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
Page 162
... PIC18F85J90 FAMILY NOTES: DS39770C-page 162 2010 Microchip Technology Inc. ...
Page 163
... LCD Clock T13CKI Source Select INTRC Oscillator INTOSC Oscillator 2010 Microchip Technology Inc. PIC18F85J90 FAMILY The LCD driver module supports these features: • Direct driving of LCD panel • On-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options • ...
Page 164
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) Maximum Number of Pixels: PIC18F6XJ90 PIC18F8XJ90 144 132 192 register, shown in Register 16-2, (LCDSE5:LCDSE0) listed in R/W-0 R/W-0 LMUX1 LMUX0 bit Bit is unknown Bias Type 48 Static 96 1/2 or 1/3 1/2 or 1/3 1/3 2010 Microchip Technology Inc. ...
Page 165
... Microchip Technology Inc. PIC18F85J90 FAMILY R-0 R/W-0 R/W-0 WA LP3 LP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 166
... LCDSE4<7:1> (SEG39:SEG33) are not implemented in 64-pin devices. 2: LCDSE5 is not implemented in 64-pin devices. DS39770C-page 166 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Segments R/W-0 R/W-0 SE SE(n) bit Bit is unknown 7:0 15:8 23:16 31:24 39:32 47:40 2010 Microchip Technology Inc. ...
Page 167
... Bits<7:1> of these registers are not implemented in 64-pin devices. Bit 0 of these registers (SEG32Cy) is always implemented. 2: These registers are not implemented on 64-pin devices. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Individual LCDDATA bits are named by the convention “SxxCy”, with “xx” as the segment number and “y” as the common number ...
Page 168
... LCD clock source or for any other purpose, LCD segment 32 become unavailable. LCDPS<3:0> 4 ÷4 00 ÷2 1:1 to 1:16 01 Programmable Prescaler ÷256 frequency of 8 MHz). OSC /4 clock OSC COM0 ÷32 ÷ COM1 or COM2 Ring Counter ÷8192 COM3 31 kHz Clock to LCD Charge Pump 2010 Microchip Technology Inc. ...
Page 169
... CKSEL<1:0>: Regulator Clock Source Select bits 11 = INTRC 10 = INTOSC 8 MHz source 01 = Timer1 oscillator 00 = LCD regulator disabled 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 16.3.2 LCD VOLTAGE REGULATOR The purpose of the LCD regulator is to provide proper bias voltage and good contrast for the LCD, regardless of V levels ...
Page 170
... M1 (Regulator without Boost the voltage BIAS for the application is expected to DD (Figure 16-3 with M0, changing BIAS will also change; where in BIAS is constant. BIAS FLY (1) 0.047 (1) 0.047 F C1 (1) 0.047 F C0 (1) 0.047 F Mode 1 BIAS DD 2010 Microchip Technology Inc. ...
Page 171
... LCDBIAS3 Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer based on the actual LCD specifications. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY configuration of the resistor ladder. Most applications using M2 will use a 1/3 or 1/2 Bias type. While Static ...
Page 172
... M3 is selected by clearing the CKSEL<1:0> and CPEN bits (2) 10 k 10 k Static Bias 1/2 Bias Bias Type Static 1/2 Bias 1 1 (1) (1) 10 k (1) 10 k (1) (1) 10 k 1/3 Bias 1/3 Bias 2010 Microchip Technology Inc. ...
Page 173
... LCDBIAS pins can be changed to increase or decrease current. As always, any changes should be evaluated in the actual circuit for its impact on the application. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY 16.4 LCD Multiplex Types The LCD driver module can be configured into four multiplex types: • ...
Page 174
... Thus, always take care to see that the V on all pixels is ‘0’ whenever Sleep mode is invoked. Figure 16-6 through Figure 16-16 provide waveforms for static, half multiplex, one-third multiplex and quarter multiplex drives for Type-A and Type-B waveforms. on all the pixels DC DC 2010 Microchip Technology Inc. ...
Page 175
... FIGURE 16-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 2010 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 SEG0 SEG1 COM0-SEG0 COM0-SEG1 1 Frame DS39770C-page 175 ...
Page 176
... PIC18F85J90 FAMILY FIGURE 16-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770C-page 176 COM0 COM1 SEG0 SEG1 1 Frame 2010 Microchip Technology Inc. ...
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... FIGURE 16-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 SEG0 SEG1 2 Frames DS39770C-page 177 ...
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... PIC18F85J90 FAMILY FIGURE 16-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770C-page 178 COM0 COM1 SEG0 SEG1 1 Frame 2010 Microchip Technology Inc. ...
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... FIGURE 16-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 SEG0 SEG1 2 Frames DS39770C-page 179 ...
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... PIC18F85J90 FAMILY FIGURE 16-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770C-page 180 COM0 COM1 COM2 SEG0 SEG2 SEG1 Frame 2010 Microchip Technology Inc. ...
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... FIGURE 16-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 COM2 SEG0 SEG1 Frames DS39770C-page 181 ...
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... PIC18F85J90 FAMILY FIGURE 16-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 DS39770C-page 182 COM0 COM1 COM2 SEG0 SEG2 SEG1 COM0-SEG0 COM0-SEG1 Frame 2010 Microchip Technology Inc. ...
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... FIGURE 16-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 COM2 SEG0 SEG1 Frames DS39770C-page 183 ...
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... PIC18F85J90 FAMILY FIGURE 16-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770C-page 184 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame 2010 Microchip Technology Inc. ...
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... FIGURE 16-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames DS39770C-page 185 ...
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... The interrupt is not generated when the Type-A waveform is selected and when the ). New data Type-B with no multiplex (static) is selected. LCD Interrupt Occurs 2 Frames T FWR Frame Boundary /2 CY /4) – ns) FRAME CY /4) – ns) FRAME CY Controller Accesses Next Frame Data FINT Frame Boundary 2010 Microchip Technology Inc. ...
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... COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution 2010 Microchip Technology Inc. PIC18F85J90 FAMILY internal oscillators (either INTRC or INTOSC as the default system clock). While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions ...
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... Select a regulator clock source using the CKSEL<1:0> bits. 7. Clear the LCD Interrupt Flag, LCDIF (PIR3<6>), and if desired, enable the interrupt by setting the LCDIE bit (PIE3<6>). 8. Enable the LCD module by setting the LCDEN bit (LCDCON<7>). 2010 Microchip Technology Inc. by setting bit ...
Page 189
... WFT BIASMD LCDREG — CPEN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for LCD operation. Note 1: These registers or individual bits are unimplemented on 64-pin devices. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE ...
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... PIC18F85J90 FAMILY NOTES: DS39770C-page 190 2010 Microchip Technology Inc. ...
Page 191
... SSPSTAT, SSPCON1 and SSPCON2 registers and select the mode prior to setting the SSPEN bit to enable the MSSP module. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY Figure 17-1 shows the block diagram of the MSSP module when operating in SPI mode. Note: Disabling the MSSP module by clearing the SSPEN (SSPCON1< ...
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... SSPBUF and the SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) the SSPBUF is not R0 R bit Bit is unknown 2010 Microchip Technology Inc. ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I 2010 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-0 (2) (3) ...
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... SSPBUF register. Additionally, the SSPSTAT register indicates the various status conditions. Note: To avoid lost data in Master mode, a read of the SSPBUF must be performed to clear the Buffer Full (BF) detect bit (SSPSTAT<0>) between each transmission. 2010 Microchip Technology Inc. ...
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... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2010 Microchip Technology Inc. PIC18F85J90 FAMILY to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the SPIOD bit (TRISG< ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...
Page 197
... Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF 2010 Microchip Technology Inc. PIC18F85J90 FAMILY driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes pull-up/pull-down resistors may be desirable depending on the application. ...
Page 198
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39770C-page 198 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 3 bit 2 bit 5 bit bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...
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... SSPOV SSPSTAT SMP CKE Legend: Shaded cells are not used by the MSSP module in SPI mode. 2010 Microchip Technology Inc. PIC18F85J90 FAMILY mode and Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. ...
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... SSPIF interrupt is set. Addr Match During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When the the SSPBUF is not 2010 Microchip Technology Inc. ...