PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet

Microcontroller

PIC18F64J90-I/PT

Manufacturer Part Number
PIC18F64J90-I/PT
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F64J90-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F64J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS39770B), the following
clarifications and corrections should be noted. Any sili-
con issues related to the PIC18F85J90 family of
devices will be reported in a separate silicon errata.
Please check the Microchip web site for any existing
issues.
REGISTER 4-1:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
IPEN
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode)
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset occurred. Must be set in software once the Reset occurs.
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Brown-out Reset occurs)
PIC18F85J90 Family Data Sheet Errata
U-0
RCON: RESET CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-1
CM
R/W-1
RI
PIC18F85J90 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
1. Module: Reset
R-1
TO
In Register 4-1: RCON: Reset Control Register, on
page 46, the register map and description for bit 5
is changed as shown in bold text.
R-1
PD
x = Bit is unknown
R/W-0
POR
80286E-page 1
R/W-0
BOR
bit 0

Related parts for PIC18F64J90-I/PT

PIC18F64J90-I/PT Summary of contents

Page 1

... BOR: Brown-out Reset Status bit Brown-out Reset has not occurred (set by firmware only Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY 1. Module: Reset In Register 4-1: RCON: Reset Control Register, on page 46, the register map and description for bit 5 is changed as shown in bold text ...

Page 2

... Status bits from the RCON register, CM, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-1. These bits are used in software to determine the nature of the Reset. © 2008 Microchip Technology Inc. ...

Page 3

... Module: Reset In Table 4-2, on page 51, CM Resets are added to the title of the fourth column. The table’s heading row appears as shown. TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY RCON Register ( ...

Page 4

... For details of bit operation, see Register 4-1. 80286E-page 4 Bit 5 Bit 4 Bit 3 Bit R/W-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Value on Details Bit 1 Bit 0 POR, BOR on page POR BOR 46, 52 0-11 11q0 R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2008 Microchip Technology Inc. ...

Page 5

... S V Rise Rate VDD DD to ensure internal Power-on Reset signal D005 V Brown-out Reset Voltage BOR Note 1: This is the limit to which V DD © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY Bit 4 Bit 3 Bit 2 RA4 RA3 RA2 LATA4 LATA3 LATA2 TRISA4 TRISA3 TRISA2 VCFG0 ...

Page 6

... Operating temperature -40°C ≤ T Min Max — 15 Conditions V = 2.0V, DD (4) = 2.0V DDCORE MHz OSC V = 2.5V, DD (PRI_IDLE mode, (4) = 2.5V DDCORE EC oscillator) ( 3.3V DD 25.3 “DC Characteristics: ≤ +85°C for industrial A Units Conditions mode when external clock is used to drive OSC1 © 2008 Microchip Technology Inc. ...

Page 7

... Code Protection Configuration Words Start-up Time from Sleep Power-up Timer Data EEPROM BOR LVD A/D Channels A/D Calibration In-Circuit Emulation © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY Memory PIC18F85J90 Family 40 MHz @ 2.15V 2.0V-3.6V Low 32 Kbytes 1,000 Write/Erase Cycles (typical) 20 Years (minimum) 43.8 μ ...

Page 8

... Register 1, bit 6 is renamed and bits 5 and 4 are changed and renamed, as shown in bold text. R/W-0 R/W-0 U-0 TXCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2008 Microchip Technology Inc. ...

Page 9

... EUSART Baud Rate Generator Register High Byte SPBRG1 EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY - Table 17-5: Registers Associated with Asynchronous Transmission ...

Page 10

... Interrupt CM Resets uuuu uuuu uuuu u-uu uuuu uuuu Value on Details Bit 1 Bit 0 POR, BOR on page 55, 233 0000 0000 WUE ABDEN 55, 232 0100 0-00 S41C3 S40C3 55, 161 xxxx xxxx 2 C™ Slave mode. See Section 16.4.3.2 “Address © 2008 Microchip Technology Inc. ...

Page 11

... Writes per Erase Cycle WE † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T ≤ ...

Page 12

... DD Min Typ Max Units — 2.5 — V μF 4.7 10 — Max Units Comments ± – 1 — dB 400 ns μs 10 — V Comments Capacitor must be low series resistance (<5 Ohms) © 2008 Microchip Technology Inc. ...

Page 13

... PORTB weak pull-up current PURB Note 1: Negative current is defined as current sourced by the pin. 2: Refer to Table 9-1 for the pins that have corresponding tolerance limits. © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T Min Max V 0 ...

Page 14

... SSPCON2 registers and select the mode prior to setting the SSPEN bit to enable the MSSP module. 80286E-page 14 2 21. Module: Figure 16-10: I C™ Slave Mode Timing (Transmission, 7-Bit Address) On page 204,the figure is replaced with the new timing diagram provided in Figure 16-10. © 2008 Microchip Technology Inc. ...

Page 15

... FIGURE 16-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY 80286E-page 15 ...

Page 16

... Waveform (Reception, 7-Bit Address) On page 221, the condition (R/W) when the Acknowledge signal (ACK) is received from the slave, after transmitting the address to the slave, is changed to ‘1’. The changed value is indicated in bold text in Figure 16-24. 80286E-page 16 © 2008 Microchip Technology Inc. ...

Page 17

... FIGURE 16-24: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY 80286E-page 17 ...

Page 18

... The POR condition should be changed to R-1 instead of R-0. The modified value is indicated in bold text in the below table. R-1 U-0 R/W-1 TX2IP — CCP2IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 U-0 CCP1IP — bit Bit is unknown © 2008 Microchip Technology Inc. ...

Page 19

... Master Mode Waveform – Reception, 7-Bit Address) and 23 (Register 8-12: IPR3). Rev E Document (12/2008) Edits were made to Data Sheet Clarification 18 (Section 25-3 “DC Characteristics: Family – Industrial). © 2008 Microchip Technology Inc. PIC18F85J90 FAMILY Specifications), Characteristics: 2 C™ Mode”), 2 C™ ...

Page 20

... PIC18F85J90 FAMILY NOTES: 80286E-page 20 © 2008 Microchip Technology Inc. ...

Page 21

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 22

... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...

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