UC3845BD1R2G ON Semiconductor, UC3845BD1R2G Datasheet - Page 9

• Manufacturer Part Number: UC3845BD1R2G
• Description: IC,SMPS CONTROLLER,CURRENT-MODE,BIPOLAR,SOP,8PIN,PLASTIC
• Manufacturer: ON Semiconductor

Specifications of UC3845BD1R2G

• Rohs Compliant: YES
• Number Of Outputs: 1
• Duty Cycle (max): 48 %
• Output Voltage: 4.9 V to 5.1 V
• Output Current: 1000 mA
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Switching Frequency: 500 KHz
• Operating Supply Voltage: 30 V
• Maximum Operating Temperature: + 70 C
• Fall Time: 50 ns
• Minimum Operating Temperature: 0 C
• Rise Time: 50 ns
• Synchronous Pin: No
• Topology: Boost, Flyback
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Undervoltage Lockout
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (V
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
upper and lower thresholds are 16 V/10 V for the UCX844B,
and 8.4 V/7.6 V for the UCX845B. The V
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX844B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 30). The UCX845B is intended for lower voltage
dc−dc converter applications. A 36 V Zener is connected as
a shunt regulator from V
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage for the
UCX844B is 11 V and 8.2 V for the UCX845B.
Output
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pulldown resistor.
pins for V
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the I
clamp level. The separate V
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of C
External
Sync
Input
Two undervoltage lockout comparators have been
These devices contain a single totem pole output stage that
The SOIC−14 surface mount package provides separate
Figure 18. External Clock Synchronization
0.01
C
(output supply) and Power Ground. Proper
T
C
to go more than 300 mV below ground.
R
47
T
T
CC
8(14)
V
4(7)
2(3)
1(1)
ref
) and the reference output (V
CC
to ground. Its purpose is to
C
EA
R
R
supply input allows the
+
Bias
Osc
2R
CC
ref
R
comparator
comparator
5(9)
ref
pk(max)
http://onsemi.com
) are
9
f +
R
R
designer added flexibility in tailoring the drive voltage
independent of V
to this input when driving power MOSFETs in systems
where V
power and control ground connections in a current−sensing
power MOSFET application.
Reference
tolerance at T
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has
short−circuit protection and is capable of providing in
excess of 20 mA for powering additional control system
circuitry.
Design Considerations
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to V
and V
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
C
A
B
6
5
2
The 5.0 V bandgap reference is trimmed to ±1.0%
Do not attempt to construct the converter on
Figure 19. External Duty Cycle Clamp and
(R A ) 2R B )C
8
ref
5.0k
5.0k
5.0k
1
1.44
CC
may be required depending upon circuit layout.
Multi−Unit Synchronization
is greater than 20 V. Figure 23 shows proper
MC1455
J
R
S
= 25°C on the UC284XB, and ±2.0% on the
Q
4
CC
D (max) +
. A Zener clamp is typically connected
3
7
R A ) 2R B
R A
8(14)
4(7)
2(3)
1(1)
To Additional
UCX84XBs
R
R
EA
+
Osc
Bias
CC
2R
5(9)
, V
R
C
,