ADNS-3000 Avago Technologies US Inc., ADNS-3000 Datasheet - Page 11

• Manufacturer Part Number: ADNS-3000
• Description: Low Power Wireless LED Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-3000

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2308-5

Table 3. AC Electrical Specifications
Electrical characteristics over recommended operating conditions. Typical values at 25° C, VDD = 1.9 V, VDD
IRLED HSDL-4261, R
11
Parameter
Motion Delay after Reset
Forced Rest Enable
Wake from Forced Rest
Power Down
Wake from Power Down
MISO Rise Time
MISO Fall Time
MISO Delay after SCLK
MISO Hold Time
MOSI Hold Time
MOSI Setup Time
SPI Time between Write
Commands
SPI Time between Write
and Read Commands
SPI Time between Read and
Subsequent Commands
SPI Read Address-Data
Delay
NCS Inactive after Motion
Burst
NCS to SCLK Active
SCLK to NCS Inactive
(For Write Operation)
SCLK to NCS Inactive
(For Read Operation)
NCS to MISO high-Z
Transient Supply Current
LED
= 36 :.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
I
DDT
MOT-RST
REST-EN
REST-DIS
PD
WAKEUP
r-MISO
f-MISO
DLY-MISO
hold-MISO
hold-MOSI
setup-MOSI
SWW
SWR
SRW
SRR
SRAD
BEXIT
NCS-SCLK
SCLK-NCS
SCLK-NCS
NCS-MISO
Min.
250
200
120
30
20
250
4
250
120
120
20
Typ.
60
40
Max.
50
1
1
50
55
200
200
120
1/f
250
60
SCLK
Units
ms
s
s
ms
ms
ns
ns
ns
ns
ns
ns
Ps
Ps
ns
Ps
ns
ns
ns
Ps
ns
mA
Notes
From RESET register write to valid motion
From Rest Mode (RM) bits set to target
rest mode
From Rest Mode (RM) bits cleared to
valid motion
From PD active (when bit 1 of register
0 x 0d is set) to low current
Through RESET register 0 x 3a.
From PD inactive to valid motion
C
C
From SCLK falling edge to MISO data valid,
no load conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK
rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data
byte, Commands to rising SCLK for last bit
of the second data byte
From rising SCLK f or last bit of the first
data byte, to rising SCLK for last bit of the
second address byte
From rising SCLK for last bit of the first data
byte, to falling SCLK for the first bit of the
next address
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read
Minimum NCS inactive time after motion
burst before next SPI usage
From NCS falling edge to first SCLK falling
edge
From last SCLK rising edge to NCS rising
edge, for valid MISO data transfer
From last SCLK rising edge to NCS rising
edge, for valid MISO data transfer
From NCS rising edge to MISO high-Z state
Max supply current during a VDD ramp
from 0 to VDD with min 150 Ps and max 20
ms rise time. (Does not include charging
currents for bypass capacitors.)
L
L
= 100 pF
= 100 pF
LED
= 1.9 V,