AD9125-M5372-EBZ Analog Devices Inc, AD9125-M5372-EBZ Datasheet - Page 24

• Manufacturer Part Number: AD9125-M5372-EBZ
• Description: 16-BIT DAC Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9125-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9125
• Features: Come With Clocking And Analog Quadrature Modulator Circuits
• Kit Contents: Quick Start Guide, Board, Software Updates
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9125
Register
Name
Sync Control 2
Sync Status 1
Sync Status 2
FIFO Control
FIFO Status 1
FIFO Status 2
Datapath Control
Address
(Hex)
0x11
0x12
0x13
0x17
0x18
0x19
0x1B
[2:0]
[7:0]
Bits
5:0
7
6
[7:0]
7
6
2
1
0
7
6
5
3
2
Name
Sync phase request[5:0]
Sync lost
Sync locked
Sync phase readback[7:0]
FIFO phase offset[2:0]
FIFO Warning 1
FIFO Warning 2
FIFO soft align
acknowledge
FIFO soft align request
FIFO reset aligned
FIFO level[7:0]
Bypass premod
Bypass sinc
Bypass NCO
NCO gain
Bypass phase compen-
sation and dc offset
−1
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Description
110 = 64.
111 = 128.
This sets the requested clock phase offset after sync.
The offset unit is in DACCLK cycles. This enables
repositioning of the DAC output with respect to the
sync input. The offset can also be used to skew the DAC
outputs between the synchronized DACs.
000000 = 0 DACCLK cycles.
000001 = 1 DACCLK cycle.
…
111111 = 63 DACCLK cycles.
1 = indicates that synchronization had been attained
but was subsequently lost.
1 = indicates that synchronization has been attained.
Indicates the averaged sync phase offset (6.2 format). If
the value differs from the requested sync phase value,
this indicates sync timing errors.
00000000 = 0.0.
00000001 = 0.25.
…
11111110 = 63.50.
11111111 = 63.75.
FIFO write pointer phase offset following FIFO reset.
This is the difference between the read pointer and the
write pointer values upon FIFO reset. The optimal value
is nominally 4.
000 = 0.
001 = 1.
…
111 = 7.
FIFO read and write pointers within ±1.
FIFO read and write pointers within ±2.
FIFO read and write pointers are aligned after a serial
port initiated FIFO reset.
Request FIFO read and write pointers alignment via the
serial port.
FIFO read and write pointers aligned after a hardware
reset.
Thermometer encoded measure of the FIFO level.
1 = bypasses f
1 = bypasses inverse sinc filter.
1 = bypasses NCO.
0 = default. No gain scaling is applied to the NCO input
to the internal digital modulator.
1 = gain scaling of 0.5 is applied to the NCO input to the
internal digital modulator. This can eliminate saturation
of the modulator output for some combinations of data
inputs and NCO signals.
1 = bypasses phase compensation and dc offset.
S
/2 premodulator.
Default
0
R
R
R
4
0
0
0
0
0
1
1
1
0
1