AD9125-M5372-EBZ Analog Devices Inc, AD9125-M5372-EBZ Datasheet - Page 50

• Manufacturer Part Number: AD9125-M5372-EBZ
• Description: 16-BIT DAC Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9125-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9125
• Features: Come With Clocking And Analog Quadrature Modulator Circuits
• Kit Contents: Quick Start Guide, Board, Software Updates
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9125
FIFO RATE MODE SYNCHRONIZATION
The Procedure for FIFO Rate Synchronization when Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in FIFO rate mode.
The procedure assumes that the REFCLK and DACCLK signals
are applied to all of the devices. The procedure must be carried
out on each individual device.
Procedure for FIFO Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
To synchronize all devices,
1.
2.
3.
Configure the device for FIFO rate mode and periodic
synchronization by writing 0x80 to the Sync Control 1
register (Register 0x10). Additional synchronization
options are available and are described in the Additional
Synchronization Features section.
Poll the sync locked bit (Register 0x12, Bit 6) to verify that
the device is back-end synchronized. A high level on this bit
indicates that the clocks are running with a constant and
known phase relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for
the time required to write two complete input data-words.
Resetting the FIFO ensures that the correct data is being
read from the FIFO of each of the devices simultaneously.
DACCLKP(1)/
DACCLKP(2)/
DACCLKN(1)
DACCLKN(2)
REFCLKP(2)/
REFCLKN(2)
FRAME2
Figure 85. FIFO Rate Synchronization Signal Timing Requirements,
DCI2
t
SKEW
t
SU_SYNC
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2× Interpolation
t
H_SYNC
To ensure that each DAC is updated with the correct data on the
same CLK edge, two timing relationships must be met on each
DAC. DCI and D[31:0] must meet the setup and hold times with
respect to the rising edge of DACCLK, and REFCLK must meet the
setup and hold times with respect to the rising edge of DACCLK.
When resetting the FIFO, the FRAME signal must be held high
for at least three data periods (that is, 1.5 cycles of DCI). When
these conditions are met, the outputs of the DACs are updated
within t
the timing requirements of the input signals is shown in Figure 85.
Figure 85 shows the synchronization signal timing with 2×
interpolation; therefore, f
shown to be equal to the FIFO rate. More generally, the maximum
frequency at which the device can be resynchronized in FIFO
rate mode can be expressed as
where N is any nonnegative integer.
f
SYNC_I
SKEW
= f
+ t
DATA
OUTDLY
/(8 × 2
of each other. A timing diagram that illustrates
N
)
DCI
= ½ × f
CLK
. The REFCLK input is