AD9276-65EBZ Analog Devices Inc, AD9276-65EBZ Datasheet - Page 38

• Manufacturer Part Number: AD9276-65EBZ
• Description: 65MSPS ADC Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9276-65EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9276
• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: *
• Power (typ) @ Conditions: 195mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9276
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9276
Table 13. Flexible Output Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
A description of the PN sequence long and how it is generated
can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value is a specific value
instead of all 1s and that the AD9276 inverts the bit stream with
relation to the ITU-T standard (see Table 14 for the initial values).
Table 14. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
See the Memory Map section for information on how to change
these additional digital output timing features through the SPI.
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 kΩ
pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an
internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
CSB Pin
This pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-up resistor that pulls this pin high and is
both 1.8 V and 3.3 V tolerant.
Initial
Value
0x0DF
0x29B80A
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
User input
1-/0-bit toggle
1× sync
One bit high
Mixed bit frequency
23
First Three Output Samples
(MSB First)
0xDF9, 0x353, 0x301
0x591, 0xFD7, 0x0A3
− 1 bits, or 8,388,607 bits.
Digital Output Word 1
N/A
1000 0000 0000
1111 1111 1111
0000 0000 0000
1010 1010 1010
N/A
N/A
1111 1111 1111
Register 0x19 and Register 0x1A
1010 1010 1010
0000 0011 1111
1000 0000 0000
1010 0011 0011
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RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a
resistor other than the recommended 10.0 kΩ resistor for RBIAS
degrades the performance of the device. Therefore, it is imperative
that at least a 1% tolerance on this resistor be used to achieve
consistent performance.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9276. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2.0 V p-p for the ADC. VREF is set internally by default, but
the VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, the AD9276 does not support
ADC full-scale ranges below 2.0 V p-p.
When applying the decoupling capacitors to the VREF pin,
use ceramic, low ESR capacitors. These capacitors should be
close to the reference pin and on the same layer of the PCB as
the AD9276. The VREF pin should have both a 0.1 μF capacitor
and a 1 μF capacitor connected in parallel to the analog ground.
These capacitor values are recommended for the ADC to
properly settle and acquire the next valid sample.
The reference settings can be selected using the SPI. The settings
allow two options: using the internal reference or using an
external reference. The internal reference option is the default
setting and has a resulting differential span of 2 V p-p.
Table 15. SPI-Selectable Reference Settings
SPI-Selected Mode
External Reference
Internal Reference (Default)
Digital Output Word 2
N/A
Same
Same
Same
0101 0101 0101
N/A
N/A
0000 0000 0000
Register 0x1B and Register 0x1C
N/A
N/A
N/A
N/A
N/A
Resulting
VREF (V)
1.0
Resulting Differential
Span (V p-p)
2 × external reference
2.0
Subject to Data
Format Select
N/A
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No