AD9276-65EBZ Analog Devices Inc, AD9276-65EBZ Datasheet - Page 42

• Manufacturer Part Number: AD9276-65EBZ
• Description: 65MSPS ADC Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9276-65EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9276
• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: *
• Power (typ) @ Conditions: 195mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9276
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9276
Table 18. AD9276 Memory Map Registers
Addr.
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Registers
0x04
0x05
0xFF
Program Function Registers
0x08
0x09
0x0D
0x0E
Register Name
chip_port_config
chip_id
chip_grade
device_index_2
device_index_1
device_update
modes
clock
test_io
GPO outputs
Bit 7
(MSB)
0
X
X
X
X
X
X
User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
X
Bit 6
LSB first
1 = on
0 = off
(default)
X
X
X
X
X
X
X
Bit 5
Soft
reset
1 = on
0 = off
(default)
Child ID[5:4]
(identify device
variants of chip ID)
00: Mode I
(40 MSPS) (default)
01: Mode II (65 MSPS)
10: Mode III (80 MSPS)
X
Clock
Channel
DCO±
1 = on
0 = off
(default)
X
X
X
Reset PN
long
gen
1 = on
0 = off
(default)
X
(AD9276 = 0x72, default)
Bit 4
1
X
Clock
Channel
FCO±
1 = on
0 = off
(default)
X
LNA
input
imped-
ance
1 = 5 kΩ
0 = 15 kΩ
(default)
X
Reset PN
short
gen
1 = on
0 = off
(default)
X
Rev. 0 | Page 42 of 48
Chip ID Bits[7:0]
Bit 3
1
X
Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
D
1 = on
(default)
0 = off
X
0
X
Output test mode—see Table 13
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by output_mode)
General-purpose digital outputs
Bit 2
Soft
reset
1 = on
0 = off
(default)
X
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
X
Bit 1
LSB first
1 = on
0 = off
(default)
X
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
X
X
Bit 0
(LSB)
0
X
Data
Channel
E
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
DCS
1 = on
(default)
0 = off
Default
Value
0x18
0x00
0x0F
0x0F
0x00
0x00
0x01
0x00
0x00
Comments
Nibbles should be
mirrored so that
LSB or MSB first
mode is set cor-
rectly regardless of
shift mode.
Default is unique
chip ID, different
for each device.
Read-only register.
Child ID used to
differentiate ADC
speed power
modes.
Bits are set to
determine which
on-chip device
receives the next
write command.
Bits are set to
determine which
on-chip device
receives the next
write command.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
generic modes
of chip operation
(global).
Turns the internal
duty cycle stabilizer
(DCS) on and off
(global).
When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, except
for PN sequence.)
Values placed on
GPO[0:3] pins
(global).