CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 30

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

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5.3
5.3.1
5.3.2
Analog Outputs
Initialization
The initialization and Power-Down sequence flow chart is shown in
enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma
modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog
and analog-to-digital converters and switched-capacitor low-pass filters are powered down.
The device remains in the power-down state until the RST pin is brought high. The control port is acces-
sible once RST is high, and the desired register settings can be loaded per the interface descriptions in
the
pins must be set up before RST is brought high. All features will default to the Hardware Mode defaults
as listed in
VQ will quickly charge to VA/2 upon initial power up. Once MCLK is valid and the PDN bit is set to ‘0’b,
the internal voltage reference, FILT+, will ramp up to approximately VA. Power is applied to the D/A con-
verters and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ.
Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK
frequency ratio. After an approximate 2000 sample period delay, normal operation begins.
Line-Level Outputs and Filtering
The CS42438 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin-
gle-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approxi-
mately VQ.
The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low-pass filter.
See
for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a
passive filter configuration which minimizes costs and the number of components.
Figure 12
VA/2.
“Control Port Description and Timing” on page
“DAC Output Filter” on page 53
shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately
Table
2.
for recommended output filter. The active filter configuration accounts
35. In Hardware Mode operation, the Hardware Mode
Figure 11 on page
311. The CS42438
CS42438
DS646F2