CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 31

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

DS646F2
No
H/W pins setup to
1. VQ = VA/2.
2. Aout bias = VA/2.
3. No audio signal generated.
Hardware Mode
desired settings.
Valid MCLK
Applied?
1. VQ = VA/2.
2. Aout = HI-Z.
3. No audio signal generated.
4. Control Port Registers reset
to default.
No
Power-Down (Power Applied)
Yes
Analog Output Mute
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Access Detected?
Control Port
RST = Low?
Control Port
No Power
Accessed
Figure 11. Audio Output Initialization Flow Chart
No
ERROR: MCLK/LRCK ratio change
Registers setup to
Software Mode
desired settings.
Valid MCLK
Yes
Applied?
Yes
ERROR: Power removed
Yes
No
RST = Low
1. VQ = VA/2.
2. Aout bias = VA/2.
3. Audio signal generated per register settings.
No
1. VQ = VA/2.
2. Aout bias = VQ.
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Sub-Clocks Applied
Normal Operation
2000 LRCK delay
PDN bit = '1'b?
MCLK/LRCK
1. VQ = VA/2.
2. Aout bias = VA/2 + last audio sample.
3. No audio signal generated.
Power-Up
Ratio?
Valid
Yes
No
ERROR: MCLK removed
Analog Output Freeze
Yes
1. VQ = VA/2.
2. Aout bias = Hi-Z.
3. No audio signal generated.
4. Control Port Registers retain
settings.
PDN bit set
to '1'b
Power-Down
CS42438
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