AS3992-BQFP-50 austriamicrosystems, AS3992-BQFP-50 Datasheet
AS3992-BQFP-50
Specifications of AS3992-BQFP-50
Related parts for AS3992-BQFP-50
AS3992-BQFP-50 Summary of contents
Page 1
... Fully scalable, the AS3992 is ideal for longer range and higher power applications. Offering DRM filtering on chip, combined with improved sensitivity and pre-distortion allows the AS3992 to be the only true world wide shippable IC. The reader configuration is achieved through setting control registers allowing fine tuning of different reader parameters. ...
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... AS3992 Data Sheet - Figure 1. AS3992 Block Diagram OAD 31 OAD_2 30 ADC 58 DAC 4 MIX_INP 7 MIX_INN 9 MIXS_IN 10 RFOUTN _1 27 RFOUTN _2 28 RFOUTP _1 20 RFOUTP _2 21 RFONX 32 Directional unit RFOPX 33 56 EXT_IN 36 OSCI 37 OSCO 60 VCO CP 62 www.austriamicrosystems.com/AS3992 4xC AS3992 IQ Down- DRM Filter Gain Filter Conversion ...
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... DA Converter ............................................................................................................................................................................. 21 7.9.2 AD Converter ............................................................................................................................................................................. 21 7.10 Reference Oscillator ......................................................................................................................................................................... 21 8 Application Information ........................................................................................................................................................... 8.1 Configuration Registers Address Space............................................................................................................................................. 22 8.2 Main Configuration Registers ............................................................................................................................................................. 24 8.3 Control Registers - Low Level Configuration Registers...................................................................................................................... 25 8.4 Status Registers ................................................................................................................................................................................. 29 8.5 Test Registers..................................................................................................................................................................................... 32 8.6 PLL, Modulator, DAC, and ADC Registers ......................................................................................................................................... 34 www.austriamicrosystems.com/AS3992 Revision 1 ...
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... QueryAdjustDown (9C)............................................................................................................................................................ 42 8.10.6 ACK (9D) ................................................................................................................................................................................. 42 8.10.7 NAK (9E).................................................................................................................................................................................. 42 8.10.8 ReqRN (9F) ............................................................................................................................................................................. 42 8.11 Reader Communication Interface ..................................................................................................................................................... 42 8.12 Parallel Interface Communication..................................................................................................................................................... 44 8.13 Serial Interface Communication ....................................................................................................................................................... 46 8.13.1 Timing Diagrams...................................................................................................................................................................... 47 8.13.2 Timing Parameters .................................................................................................................................................................. 48 8.14 FIFO ................................................................................................................................................................................................. 48 9 Package Drawings and Markings ........................................................................................................................................... 10 Ordering Information............................................................................................................................................................. www.austriamicrosystems.com/AS3992 Revision 1 ...
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... DAC 4 VDD_5LFI 5 VSS 6 MIX_INP 7 VSS 8 MIX_INN 9 www.austriamicrosystems.com/AS3992 AS3992 Pin Type Bidirectional Connect de-coupling capacitor to VDD_5LFI Bidirectional Bidirectional DAC output for external amplifier support, Output Resistance of DAC pin is Output 1kΩ Positive supply for LF input stage, connect to VDD_MIX Supply Input Substrate Supply Input ...
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... IO0 41 IO1 42 IO2 43 IO3 44 IO4 45 www.austriamicrosystems.com/AS3992 Pin Type Single ended mixer input Input Supply Input Mixer negative supply Internal node de-coupling capacitor to GND Bidirectional Mixer positive supply, internally regulated to 4.8V Internal node de-coupling capacitor to VDD_MIX Bidirectional Power Amplifier Bias positive supply. Connect to VDD_MIX Supply Input Main positive supply input ( ...
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... VOSC VDDLF 63 COMP_A 64 EXP_PAD 65 www.austriamicrosystems.com/AS3992 Pin Type I/O pin for parallel communication Bidirectional Sub-carrier output in case of direct mode I/O pin for parallel communication. MISO in case of serial communication (SPI) Bidirectional Sub-carrier output in case of direct mode I/O pin for parallel communication. Bidirectional MOSI in case of serial communication (SPI) ...
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... Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet the published specifications. RF integrated circuits are also more susceptible to damage due to use of smaller protection devices on the RF pins, which are needed for low capacitive load on these pins. www.austriamicrosystems.com/AS3992 Electrical Characteristics on page 9 Min ...
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... Logic Input/Output Max. CLK frequency V Input logic low LOW V Input logic high HIGH R Output resistance IO0…IO7 IO R Output resistance CL SYS CL SYS www.austriamicrosystems.com/AS3992 Conditions V Consumption EXT V Consumption, EXT2 V = 2.5V DD_RF All system disabled including supply voltage regulators The difference between the external ...
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... Data Sheet - Table 4. Recommended Operating Conditions Symbol Parameter Supply Voltage Supply voltage (bit vext_low set) Operating virtual junction temperature T J range T Ambient temperature AMB Rth junction to exposed die pad www.austriamicrosystems.com/AS3992 Conditions Min 5.0 4.1 -40 -40 Revision 1.0 Typ Max Units 5.3 5.5 V ...
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... An additional 4.8V regulator is used for the input RF mixers supply. The input of this regulator is VEXT, output is VDD_MIX pin. For correct operation of the 4.8V regulator, the VEXT voltage needs to be between 5.3V and 5.5V. VDD_MIX needs de-coupling capacitors to VDD_MIX like other VDD pins. www.austriamicrosystems.com/AS3992 about operation of the EN pin). At power-up, the configuration registers are preset to a Configuration Registers Address Space on page 22 ...
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... Using this function, the superior system can wake up the reader IC and MCU that are both in the power down mode. If the MCU during 200µs period finds out that the RFID system must react, it confirms the normal mode by setting EN high. Table 5. AS3992 Power Modes Power mode ...
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... VCO output level to other RF circuitry demands. VCO and CP pin valid range is between 0.5V and 2.9V. AS3992 has internal VCO set to a frequency range around 1800MHz, later internally divided by two for decreasing the VCO pulling effect. The tuning curve of 1800MHz VCO is divided into 16 segments to decrease VCO gain and attain lowest possible phase noise. ...
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... RX option 40 kHz Link frequency <7:4> (0000) www.austriamicrosystems.com/AS3992 (see Table 25). By reading this register, the host system is notified by the cause of the store the number of complete bytes that should be transmitted. Bit B0 (in register 1E flag (see Table 14). As defined by selected protocol, the reader automatically Individual Settings 12.5µ ...
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... MISO in SPI mode is used as direct mode data or subcarrier output possible to write register 00 to terminate the direct mode. After direct mode termination, normal communication via SPI interface and access to the registers are possible. For more information on transmit modulation input signal possibilities, refer to www.austriamicrosystems.com/AS3992 25µs 2.5 ...
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... RFOUT_1 and RFOUT_2. Single ended output is RFOUT_1. UHF - power amplifiers (PAs) are generally sensitive to parasitics (layout, placement, routing, PCB material etc) and load conditions. We recommend to carefully investigate the specific system implementation on inherent parasitic and load variations to avoid instabilities over production. www.austriamicrosystems.com/AS3992 TX Pre-Distortion on page 15. ...
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... LF -order high-pass Chebyshev filter with adjustable -1dB from 72kHz to 200kHz. The filter can also be reconfigured to 1 frequency at 5.5kHz or 12kHz for lower LF and FM0 coding. www.austriamicrosystems.com/AS3992 Supply on page 11), the low_vext option bit adapts mixer’s operation point to (see Table 23). ...
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... Such a system is needed to accommodate the short time used at the highest bit rates in the EPC Gen 2 protocol possible to additionally speed up the first AC coupling time constant by setting option bit lf4_ac_su in the ‘Test register’ (12). www.austriamicrosystems.com/AS3992 -3dB low-pass frequency Atten. at 40kHz ...
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... To relieve the host system (MCU) of reading RN16 (or handle) out of the FIFO and then writing it back into the FIFO, there is a special register for storing last received RN16 during the Query, QueryRep, QueryAdjust or RegRN commands. The last stored RN16 is automatically used in ACK command. www.austriamicrosystems.com/AS3992 (see Table (see Table 14) and Rx_LF< ...
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... RX length is not known in advance is reception of the PC+EPC. AS3992 handles the issue mentioned above by using special RX mode. The idea is that reader chip generates an additional interrupt after two bytes (PC part of the PC+EPC field) are received. MCU reads out the two bytes that define the length of the on going telegram and writes it in the RX length register ...
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... OSCO pin. The signal should be sinusoidal shape, 1Vpp, DC level 1. coupled. www.austriamicrosystems.com/AS3992 ADC Interface RSSI AS3992 (see Table 40) and the output pin is DAC. Output range two (see Table 41). AD converter can also be used for measuring the mixers DC output ADCreg = [(VEXT-1.6)*0.8-1.6] / 0.0126 Revision 1 ...
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... Regulator and IO control TX pre-distortion (deep register) 13 CL_SYS, analog out, and CP 14 Modulator control (3 bytes deep) 15 www.austriamicrosystems.com/AS3992 Display microcontroller Optional Tx 8 I/O IRQ CLK CLSYS VCC PA UHF Reader AS3992 Rx Optional VCO Register Register Revision 1.0 Length R/W 1 R/W 1 Length R/W 1 R/W 1 R/W ...
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... Table 11. Test Registers Adr (hex) Measurement selection 11 Test setting 12 Table 12. FIFO Registers Adr (hex) RX length 1A RX length 1B 1C FIFO status TX length byte1 1D TX length byte2 1E FIFO I/O register 1F www.austriamicrosystems.com/AS3992 Register R/W R/W R/W R Register R R Register R/W R/W Register R/W R/W R R/W ...
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... B3 RX_cod1 B2 RX_cod0 B1 Tari1 B0 Tari0 1. Preset to 06 (Gen2, Miller2, Tari=25µs) at EN=L or POR=H www.austriamicrosystems.com/AS3992 Function 0: normal mode Stand-by power mode 1: stby power mode External modulation control for transmission and IQ or Direct data mode bit stream output for reception 0: DAC off DA converter enable ...
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... B7 Rx_LF3 B6 Rx_LF2 B5 Rx_LF1 B4 Rx_LF0 B3 pil_meas_sh<1:0> TRext B0 1. Preset at POR=H or EN=L Gen2: 60 (160kHz) www.austriamicrosystems.com/AS3992 Function 00: 0.27Tari 01: 0.35Tari PW length control 10: 0.44Tari 11: 0.50Tari 00: 1.50Tari 01: 1.66Tari TX one length control 10: 1.83Tari 11: 2.00Tari 0: CRC-16 TX CRC type 1: CRC-5 Normally TRcal is automatically transmitted when Query (98) direct command is issued, according to EPC Gen2 and ISO18000-6C ...
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... B3 TRcal11 B2 TRcal10 B1 TRcal9 B0 TRcal8 1. Preset at POR=H or EN=L Gen2: 05 www.austriamicrosystems.com/AS3992 Function Gen2: 17.2µs…225µs TRcal range 0.1µs…409µs (1…4096 steps) step size 0.1µs worst case relative resolution (0.1µs/ 17.2µs=0.6%) 1 Function 0: Decrease RX gain direction 1: Increase gain by option bits gain<5:4> in reg0A 0: 4 ...
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... Rxw2 B1 Rxw1 B0 Rxw0 1. Preset at POR=H or EN=L Gen2: 07(44.8µs < 54.25µs…84.5µs – LF:160kHz) www.austriamicrosystems.com/AS3992 1 Function TX reply range 6.4µs to 1632µs (1…255), Start at end of RX. 00: Delayed transmission is disabled. Delayed transmission wait time Gen2: T2=4.68µs…500µs after end of RX, Select T4> ...
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... B3 gain<0> B2 s_mix B1 ir<1> B0 ir<0> 1. Preset to 01 (Max gain, mixer range) at POR=H or EN=L www.austriamicrosystems.com/AS3992 Function Bypass for 160kHz LF Bypass for 40kHz LF Low pass setting see DRM RX Filter on page 17 High pass setting Function Gain change, 3 steps by 3dB, Increase/decrease RX gain setting defined by gain<3> option bit in reg05 ...
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... Irq_2 _byte B2 Irq_err2 Irq_err3 / B1 Irq_RX_finished B0 Irq_noresp 1. Preset POR=H or EN= automatically reset at the end of read phase. The reset also removes the IRQ flag. www.austriamicrosystems.com/AS3992 Function for VDD_RF current source 00: 2V 01: 2.5V Internal power amplifier regulator setting 10: 3V 11: 3.5V 0: RFOUT1 only PA2 enable ...
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... Function IRQ enabled by default When enabled, AS3992 will generate an active high Interrupt when the FIFO is getting low (6 Bytes left to send on transmit operation getting full over 18 bytes on receive operation. When enabled, AS3992 will generate an active high Interrupt when the device detects an CRC error (This option will report no crc error when receive without crc is enabled) ...
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... B4 vco_ri<4> B3 vco_ri<3> B2 vco_ri<2> B1 vco_ri<1> B0 vco_ri<0> www.austriamicrosystems.com/AS3992 Function RSSI value of Q channel (REC_B) (16 steps, 2dB per step) RSSI value of I channel (16 steps, 2dB per step) (REC_A) Function AGL status - REC_A 7 steps, 3dB per step AGL status - REC_B 7 steps, 3dB per step ...
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... AGL / VCO / F_CAL / PilotFreq Status Register (10) – in case r10page<2:0>=3 (reg12) displays the result of RX filter calibration. Table 32. AGL / VCO / F_CAL / PilotFreq Status Register (10) Bit Signal Name pilot_freq<7:0> Version Register (13) 30: AS3990 38: AS3991 51: AS3992 8.5 Test Registers Measurement Selection (11) 1 Table 33. Measurement Selection (11) Bit Signal Name msel<3> B2 msel<2> B1 msel< ...
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... AGC mode type 1: enables changing of hp cal. with 89 and 8A. Change the RX filter calibration 0: enables changing of lp cal. Result in reg10. First stage AC coupling speed-up RX settling speed up (2x in AS3992, it was fl<4> in reg09) rfu Miller decoder mode Set to 0 for correct operation Subcarrier input Subcarrier output For test purposes only ...
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... VCO frequency dependence 2:0 cp<2:0> Charge pump current 1. Preset at POR=H or EN=L Default setting (Medium VCO bias, CLSYS: 5MHz, min. CP current) www.austriamicrosystems.com/AS3992 1 Function 00 – normal operation with auto power saving mode 01 – External sinus TCXO AC coupled to OSCO 10 – Disable auto power saving mode cp< ...
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... TX output level fine adjustment 1. Preset at POR=H and EN=L Default: set (aux. modulation, ASK, level nominal) www.austriamicrosystems.com/AS3992 Function 0: IO3 is digital modulation input in direct mode. 1: ADC is analog mod. input in direct mode (allowed when ADC not used). Should be low for normal operation ...
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... B5 dac<5> B4 dac<4> B3 dac<3> B2 dac<2> B1 dac<1> B0 dac<0> 1. Default: reset POR=H and EN=L www.austriamicrosystems.com/AS3992 1 Function Increase internal PA bias Increase two times 000: 500kHz 001: 250kHz 100: 200kHz PLL reference divider 010: 125kHz 101: 100kHz 110: 50kHz 111: 25kHz Prescaler 32/33, PLL main divider dividing ratio N=B*32+A*33, proposed A/B ratio: 1/ 3… ...
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... B1 rxl<1> B0 rxl<0> 1. Default: reset POR=H, EN=L, at the end of reception. www.austriamicrosystems.com/AS3992 Function Via ADC the two mixers output DC levels can be measured showing the reflectivity of the antenna or the environment. Also DC level on ADC pin can be measured. The later case can be used for checking the RF output power via external power detector ...
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... B2 Txl6 B1 Txl5 B0 Txl4 1. Default: reset POR=H and EN= also automatically reset at TX EOF www.austriamicrosystems.com/AS3992 Function High FIFO level Indicates that 18 bytes are in FIFO already (for RX) Low FIFO level Indicates that only 6 bytes are left in FIFO (for TX) FIFO overflow error Several data is written to FIFO ...
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... Block RX Enable RX 97 Query (=TX with TX CRC5 CRC) 98 QueryRep (= CRC CRC) 99 www.austriamicrosystems.com/AS3992 Function number of complete byte– bn[3] number of complete byte– bn[2] number of complete byte– bn[1] number of complete byte– bn[0] broken byte number of bits bb[2] broken byte number of bits bb[1] ...
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... Transmission starts when the third byte is written in the FIFO. Transmission of short messages (less than three bytes) is started when complete data is in the FIFO. When the command is received the reader starts transmitting. CRC-16 is included in the transmitted sequence. In this mode the micro controller has control on precise timing. www.austriamicrosystems.com/AS3992 Command (see Table (see Table Revision 1 ...
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... The QueryAdjustNic command issues the command QueryAdjust followed by two session bits and ‘no change’ parameter. The session bits are taken from ‘TX options’ (02) register. The received RN16 is stored in an internal register for further communication (ACK also achievable from the FIFO. www.austriamicrosystems.com/AS3992 (see Table Revision 1.0 19) ...
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... A/D[1] IO1 A/D[0] IO0 IRQ IRQ interrupt 1. SS – Slave Select pin active low 2. MOSI – Master Output, Slave Input 3. MISO – Master Input, Slave Output www.austriamicrosystems.com/AS3992 Parallel normal mode, Direct mode SCLK from master 2 MOSI 3 MISO Direct mode out (sub-carrier) Direct mode out (sub-carrier) SS – ...
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... There are also combinations of different communication modes allowed in a single stream between the start and stop condition. Some examples of combined communication are presented below: Non-continuous Address Mode and Command Mode Start Adr x Data (x) www.austriamicrosystems.com/AS3992 48. Communication is closed by an appropriate stop condition. Three different communication Bit Function 0=Address, 1=Command 1=Read, 0=Write 1=Cont., 0=Non-cont mode ...
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... IO7 pin while CLK pin is high and IO6-IO0 are low. StopCont condition is triggered by successive rising and falling edge on IO7 pin while CLK and IO6-IO0 are low. The ‘StopSgl’ condition is used to terminate the direct mode. Figure 6. Parallel Interface Communication with Single Stop Condition “StopSgl” Start condition CLK IO7 a1[6:0] IO[6:0] www.austriamicrosystems.com/AS3992 … Adrc z Data (z) Data (z+1) … Adrc z Data (z) ...
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... To decrease interferences between MCU communication and RF part of the chip, the output resistance of IO0…IO7 lines is 400Ω typical and 800Ω maximum. The firmware designer should be aware of the fact that in case higher capacitance are connected to these pins, then possibly longer CLK high intervals are needed to allow settling of the output level. www.austriamicrosystems.com/AS3992 d0[7] d1[7] ...
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... The firmware designer should be aware that in case of higher capacitance is connected to this pin possibly longer CLK high interval is needed to allow settling of the output level. Minimum time interval between bytes is 200ns. Minimum time interval between last CLK falling edge and IO4 rising edge is 200ns. Minimum IO4 high time interval is 200ns. www.austriamicrosystems.com/AS3992 ...
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... AS3992 Data Sheet - 8.13.1 Timing Diagrams Figure 10. Write Data ENABLE - IO4 t CHD CLK MOSI - IO7 DATAO Figure 11. Read Data ENABLE - IO4 CLK MOSI - IO7 DATAI MISO - IO6 www.austriamicrosystems.com/AS3992 DIS DIH DATAI DATAI DOD DATAI t DOH DATAO ( Revision 1 DATAI t DOD DATAO ( ...
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... FIFO status register. This register also contains three status flags: Fove bit is set in case of FIFO overflow Flol bit is set in case of low FIFO level during transmission Fhil bit is set in case of high FIFO level during reception www.austriamicrosystems.com/AS3992 Condition Min 250 250 ...
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... Figure 12. Package Drawings 48 33 Table 51. Package Dimensions Symbol Min Nom A 0.80 0. 0.203 REF b 0.18 0.23 D 9.00 BSC E 9.00 BSC D2 5.90 6.00 E2 5.90 6.00 www.austriamicrosystems.com/AS3992 Max Symbol 0. 0.28 aaa bbb ccc 6.10 ddd 6.10 eee Revision 1.0 Min Nom Max ...
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... AS3992 Data Sheet - Revision History Revision Date 1.0 Dec 21, 2009 Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com/AS3992 Owner tlu Initial revision Revision 1.0 Description ...
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... Dry Pack sensitivity Level =3 according to IPC/JEDEC J-STD-033A. Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: For further information and requests, please contact us or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/AS3992 Table 52. Description Delivery Form Tape and Reel in dry pack http://www ...
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... No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/AS3992 Revision 1 ...