CORR-8BIT-XM-U2 Lattice, CORR-8BIT-XM-U2 Datasheet
CORR-8BIT-XM-U2
Specifications of CORR-8BIT-XM-U2
Related parts for CORR-8BIT-XM-U2
CORR-8BIT-XM-U2 Summary of contents
Page 1
... Introduction The function of this core is to correlate an incoming data stream to a stored binary pattern called a code sequence or coefficient sequence. The data stream ...
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... The basic correlator equation is given by: The terms of the equation are: • d – Input data sequence. The Correlator IP core allows the input sequence to be from bits wide, and either i signed (two’s complement) or unsigned data. • c – ...
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... Correlator Input and Output Data The Correlator IP core accepts a new input data value for a channel and writes that value into Tap Memory. When it is ready to perform the next correlation operation for that channel, the new data value will be included in the corre- lation, along with enough “ ...
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... At time 178.5µs, crdy again goes active indicating that the Correlator IP core is ready to accept the next input value, and in the example of Figure 2 the user inputs data for channel 1. At time 196.5µs, the correlation result for channel 0 is ready at the dout outputs, and the core outputs a value of 0x9 on dout , sets the chan_out to 0, and asserts the ordy signal. It also asserts the block_start_out signal to indicate that this output value was asso- ciated with the din value from time 175.5µ ...
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... EBR blocks in the design based on the parame- ters selected by the user. In the case of the Tap Memory, the number of correlator cells, number of taps, number of channels, and the oversampling rate all determine how many EBR memories are needed. The number of correlator cells (parameter MWIDTH) determines how many words of data can be operated on during a single clock cycle. The more correlator cells which are confi ...
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... In the example above, the first four values written are for coefficient sequence 0. The values writ- ten are 0xa6fc (or in binary: 1010 0110 1111 1100) with the LSB being the first bit in the correlation sequence. This bit will be multiplied against the newest data value received by the Correlator. The MSB in this string will be multi- plied against the oldest data read from Tap Memory ...
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... For example, if the number of taps is eight and an oversampling rate of two is chosen, then the circuit will correlate the eight coefficient values with the newest input tap data value and the odd numbered tap data values from the past 15 “ ...
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... If the FIFO depth is set above 1, then the user must insure that a new data sample will not be presented to the Correlator IP core for the same channel as is presently being serviced or the new data sample will be written into the core’s internal tap memory and will corrupt the correlation which is already in progress for that channel. If the core has been confi ...
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... For core configurations that are not available in the Evaluation Packages, please contact your Lattice sales repre- sentative to request a custom configuration. Related Information For more information regarding core usage and design verification, refer to the Parallel RapidIO Physical Layer Interface IP Core User’s Guide, available on the Lattice web site at www.latticesemi.com. 9 Correlator IP Core ...
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... IP core in a different density, speed, or grade within the Lattice ECP/EC family, performance may vary. Supplied Netlist Configurations The Ordering Part Number (OPN) for the Correlator IP Core on LatticeECP/EC devices is CORR-8BIT-E2-N1 (for all configurations of the netlist package). Table 3 lists the evaluation netlists that can be downloaded from the Lat- tice web site at www.latticesemi.com. To load the preset parameters for this core, click on the “ ...