LS-HDL-PRO-PCM-N Lattice, LS-HDL-PRO-PCM-N Datasheet - Page 3

• Manufacturer Part Number: LS-HDL-PRO-PCM-N
• Description: Development Software Maintenance LS-HDL-PRO-PC-N
• Manufacturer: Lattice

Specifications of LS-HDL-PRO-PCM-N

• Tool Function: Compiler
• Tool Type: Compiler
• Processor Series: Lattice FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Key Features, Cont.
more. Completing your design can be as simple as double-
clicking the task you want to perform and letting ispLEVER
do the rest.
Power Calculator
The ispLEVER Power Calculator includes an environment-
aware power model, graphical power displays and a variety
of useful reports. Thermal resistance options model real
world thermal conditions, including heatsinks, airflow, and
the printed circuit board complexity, while graphical power
curves illustrate operating temperature profiles.
FPGA Design Planner
The Design Planner is a centralized interface where you
Design Planner: Package View + SSO Analyzer
can perform all floorplanning, path analysis, I/O assign-
ment, PLL definition, and other implementation tasks. Also
included is the unique SSO Analyzer to check noise caused
by parallel I/O switching. All design preferences are stored
in a centralized database file, which can be edited from any
point in the design process.
Simulink Blockset – ispLeverDSP
ispLEVER includes DSP blocks that can be used to build
DSP solutions within the MATLAB/Simulink environment.
These solutions can then be exported in HDL optimized for
Lattice FPGA architectures.
IPexpress
IPexpress is the interface to the Lattice catalog of functional
FPGA Design Planner
modules, reference designs, and intellectual property (IP),
all optimized for Lattice programmable products. IPexpress
accelerates the design process by helping you smoothly con-
figure and integrate these functions into your design.
Performance Analyst™ Timing Analyzer
Performance Analyst is a powerful static timing analyzer that
allows users to rapidly analyze critical timing requirements
and experiment with devices of differing speed grades with-
out recompiling the design.
HTML-Based Reporting
Report viewing is made easy using standard web browsers.
Reveal Logic Analyzer
The Reveal Logic Analyzer uses a signal-centric model for
HDL Explorer
embedded logic debug; the user first defines signals of
interest and the Reveal tool then inserts the instrumentation
along with the proper connections to enable the required
observations. The ability to specify complex, multi-event
triggering sequences makes system-level design debug
smoother and faster.
HDL Explorer
HDL Explorer generates graphic representations of your
HDL’ s hierarchical structure and connectivity. You can use
intelligent tools to cross-probe between views, pinpoint
Reveal Logic Analyzer
problems and more.