XR21V1414IM-0B-EB Exar Corporation, XR21V1414IM-0B-EB Datasheet
XR21V1414IM-0B-EB
Specifications of XR21V1414IM-0B-EB
Related parts for XR21V1414IM-0B-EB
XR21V1414IM-0B-EB Summary of contents
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SEPTEMBER 2010 GENERAL DESCRIPTION The XR21V1414 (V1414 enhanced 4-channel USB Universal Asynchronous Transmitter (UART). The USB interface is fully compliant to Full Speed USB 2.0 specification that supports 12 Mbps USB data transfer rate. The USB interface also ...
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XR21V1414 4-CH FULL-SPEED USB UART F 1. XR21V1414 B D IGURE LOCK IAGRAM 3.3V VCC GND USB Slave USBD+ Interface USBD- 2 SDA I C SCL Interface Internal 48MHz Oscillator 128-byte TX FIFO Fractional BRG 384-byte RX FIFO Internal Status ...
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... REV. 1.1 IGURE IN UT SSIGNMENT GPIOD0/RID# TXD RXD GND GND USBD- USBD+ VCC VCC GPIOD5/RTSD# GPIOD4/CTSD# GPIOD3/DTRD# ORDERING INFORMATION P N ART UMBER XR21V1414IM48 48-pin TQFP XR21V1414 42 48-TQFP ACKAGE PERATING EMPERATURE -40° +85° XR21V1414 4-CH FULL-SPEED USB UART GPIOC5/RTSC# 24 RXC 23 TXC 22 21 ...
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XR21V1414 4-CH FULL-SPEED USB UART PIN DESCRIPTIONS Pin Description 48-QFN N AME UART Channel A Signals RXA 31 TXA 30 21 GPIOA0/RIA# 20 GPIOA1/CDA# 17 GPIOA2/DSRA# 16 GPIOA3/DTRA# 7 GPIOA4/CTSA# 6 GPIOA5/RTSA# UART Channel B Signals RXB ...
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REV. 1.1.0 Pin Description 48-QFN N AME TXB 8 15 GPIOB0/RIB# 14 GPIOB1/CDB# 13 GPIOB2/DSRB# 12 GPIOB3/DTRB# 11 GPIOB4/CTSB# 10 GPIOB5/RTSB# UART Channel C Signals RXC 23 TXC 22 29 GPIOC0/RIC# T YPE O UART Channel B ...
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XR21V1414 4-CH FULL-SPEED USB UART Pin Description 48-QFN N AME GPIOC1/CDC# 27 GPIOC2/DSRC# 26 GPIOC3/DTRC# 25 GPIOC4/CTSC# 24 GPIOC5/RTSC# UART Channel D Signals RXD 39 TXD 38 37 GPIOD0/RID# 34 GPIOD1/CDD# T YPE I/O UART Channel ...
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REV. 1.1.0 Pin Description 48-QFN N AME GPIOD2/DSRD# 48 GPIOD3/DTRD# 47 GPIOD4/CTSD# 46 GPIOD5/RTSD# USB Interface Signals USBD+ 43 USBD- 42 I2C Interface Signals SDA 35 SCL 36 T YPE I/O UART Channel D general purpose ...
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XR21V1414 4-CH FULL-SPEED USB UART Pin Description 48-QFN N AME Miscellaneous Signals 2 LOWPOWER 5, 18, 33, VCC 44 19, GND 32, 40 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open ...
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REV. 1.1.0 1.0 FUNCTIONAL DESCRIPTIONS 1.1 USB interface The USB interface of the V1414 is compliant with the USB 2.0 Full-Speed Specifications. The USB configuration model presented by the V1414 to the device driver is compatible to the Abstract Control ...
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XR21V1414 4-CH FULL-SPEED USB UART 1.3 I2C Interface The I2C interface provides connectivity to an external I2C memory device (i.e. EEPROM) that can be read by the V1414 for configuration. The SDA and SCL are used to specify whether Remote ...
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REV. 1.1.0 Bit 6 is Self-powered mode - set to ’0’ for bus-powered, set to ’1’ for self-powered Bit 5 is Remote Wakeup support - set to ’0’ for no support, set to ’1’ for remote wakeup support Bit 4:0 ...
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XR21V1414 4-CH FULL-SPEED USB UART bit m ode 1st byte 2nd byte 1st byte ...
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REV. 1.1 RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts ...
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XR21V1414 4-CH FULL-SPEED USB UART 1.5.7.1 Receiver If an address match occurs in either flow control mode the address byte will not be loaded into the RX FIFO, but all subsequent data bytes will be loaded into ...
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REV. 1.1.0 2.0 USB CONTROL COMMANDS The following table shows all of the USB Control Commands that are supported by the V1414. Commands included are standard USB commands, CDC-ACM commands and custom Exar commands ABLE R EQUEST N ...
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XR21V1414 4-CH FULL-SPEED USB UART T ABLE R EQUEST N AME T YPE CDC_ACM_IF 0x21 SEND_BREAK XR_SET_REG 0x40 XR_GETN_REG 0xC0 2.1 UART Block Numbers The table below lists the block numbers for accessing each of the UART channels and the ...
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REV. 1.1.0 3.0 REGISTER SET DESCRIPTION The internal register set of the V1414 consists of 3 different blocks of registers: the UART Manager, UART registers and UART miscellaneous registers. The UART Manager controls the TX and RX enables and FIFOs ...
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XR21V1414 4-CH FULL-SPEED USB UART 3.2 UART Register Map DDRESS EGISTER AME 0X00 Reserved 0X01 Reserved 0X02 Reserved 0X03 UART_ENABLE 0X04 CLOCK_DIVISOR0 0x05 CLOCK_DIVISOR1 0x06 CLOCK_DIVISOR2 0x07 TX_CLOCK_MASK0 0x08 TX_CLOCK_MASK1 0x09 RX_CLOCK_MASK0 0x0A RX_CLOCK_MASK1 0x0B CHARACTER_FORMAT 0x0C ...
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REV. 1.1.0 3.3 UART Register Descriptions 3.3.1 UART_ENABLE Register Description (Read/Write) This register enables the UART TX and RX. For proper functionality, the UART TX and RX must be enabled in the following order: FIFO_ENABLE_CHx = 0x1 UART_ENABLE = 0x3 ...
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XR21V1414 4-CH FULL-SPEED USB UART ABLE LOCK IVISOR AND AUD ATE BPS LOCK 1200 2400 4800 9600 19200 38400 57600 115200 230400 460800 500000 576000 921600 1000000 1152000 1500000 2000000 2500000 ...
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REV. 1.1 NDEX ECIMAL ...
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XR21V1414 4-CH FULL-SPEED USB UART 3.3.5 CHARACTER_FORMAT Register Description (Read/Write) This register controls the character format such as the word length ( 9), parity (odd, even, forced ’0’, or forced ’1’) and number of stop bits (1 or ...
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REV. 1.1.0 FLOW_CONTROL[2:0]: Flow control mode select T ABLE ODE ...
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XR21V1414 4-CH FULL-SPEED USB UART 3.3.8 ERROR_STATUS Register Description - Read-only This register reports any errors that may have occurred on the line such as break, framing, parity and overrun. ERROR_STATUS[2:0]: Reserved These bits are reserved. Any values read from ...
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REV. 1.1.0 3.3.11 GPIO_MODE Register Description (Read/Write) GPIO_MODE[2:0]: GPIO Mode Select There are 4 modes of operation for the GPIOs. The descriptions can be found in page 11. BITS GPIO0 GPIO1 GPIO2 [2:0] 000 GPIO0 GPIO1 GPIO2 001 GPIO0 GPIO1 ...
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XR21V1414 4-CH FULL-SPEED USB UART 3.3.14 GPIO_SET Register Description (Read/Write) Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ bit has no effect. Bits 7-6 are unused and should be ’0’. 3.3.15 GPIO_CLEAR ...
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REV. 1.1.0 3.4.1 WIDE_MODE Register Description (Read/Write) This register enables the Wide mode functionality for the UART. WIDE_MODE[0]: Enable wide mode Logic 0 = Normal ( bit data) mode Logic 1 = Wide mode - See “Section ...
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XR21V1414 4-CH FULL-SPEED USB UART Logic 0 = Disable GPIO4 status in custom interrupt packet. Logic 1 = Enable GPIO4 status in custom interrupt packet. CUSTOM_INT_PACKET[6]: GPIO5 Logic 0 = Disable GPIO5 status in custom interrupt packet. Logic 1 = ...
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REV. 1.1.0 If the Exar vendor specific packet mapping is enabled then the data field also includes status for all of the UART / GPIO pins as follows ABLE ATA IELD ...
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XR21V1414 4-CH FULL-SPEED USB UART 4.0 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS - POWER CONSUMPTION -40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER I Power Supply Current CC I Suspend mode Current Susp DC ELECTRICAL CHARACTERISTICS - ...
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REV. 1.1.0 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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... Clarified pin functionality, wide mode and low latency mode including registers / blocks, clarified FLOW_CONTROL and GPIO_MODE register functionality. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...