XRT72L53ES-75L03D-PCI Exar Corporation, XRT72L53ES-75L03D-PCI Datasheet

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XRT72L53ES-75L03D-PCI

Manufacturer Part Number
XRT72L53ES-75L03D-PCI
Description
Interface Modules & Development Tools Evaluation Board for XRT72L53 Series
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT72L53ES-75L03D-PCI

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MAY 2001
GENERAL DESCRIPTION
The XRT72L53, 3 Channel DS3/E3 Framer IC is de-
signed to accept User Data from the Terminal Equip-
ment and insert this data into the Payload bit-fields
within an Outbound DS3/E3 Data Stream. Further,
the Framer IC is also designed to receive an Inbound
DS3/E3 Data Stream (from the Remote Terminal
Equipment) and extract out the User Data.
The XRT72L53 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 (November 1995 and October 1998 Re-
visions) Framing Formats.
The XRT72L53 DS3/E3 Framer IC consists of three
Transmit sections, three Receiver sections, three Per-
formance Monitor Sections and a Microprocessor in-
terface.
The Transmit Sections, include a Transmit Payload
Data Input Interface block, a Transmit Overhead Data
Input Interface block, a Transmit HDLC Controller, a
Transmit DS3/E3 Framer block and a Transmit LIU In-
terface Block which allows the Terminal Equipment to
transmit data to a remote terminal.
The Receive Sections, consist of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows
Exar
F
IGURE
Corporation 48720 Kato Road, Fremont CA, 94538
1. B
LOCK
RxOHEnable[n:0]
RxOHFrame[n:0]
RxLineClk[n:0]
TxLineClk[n:0]
RxOHClk[n:0]
TxOHEnable
TxOHFrame
RxNEG[n:0]
RxOOF[n:0]
TxNEG[n:0]
RxPOS[n:0]
NibbleLnTF
TxPOS[n:0]
RxRed[n:0]
RxOH[n:0]
TestMode
TxOHClk
TxAISEn
TxOHIns
D
ExtLOS
TxOH
IAGRAM OF THE
Overhead
Transmit
Interface
Controller
Overhead
Interface/
Interface
Receive
T3/E3
T3/E3
LIU
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L53
PRELIMINARY
T3 FEAC & Data
T3/E3 Transmit
Link Controller
T3/E3 Receive
Framer
Framer
Where n = 0, 1 & 2
Typical Channel n
(510) 668-7000
Performance
Monitor
the local terminal equipment to receive data from re-
mote terminal equipment.
The Microprocessor Interface is used to configure the
Framer in different operating modes and monitor the
performance of the Framer.
The Performance Monitor Sections consist of a large
number of Reset-upon-Read and Read-Only regis-
ters that contain cumulative and One-Second statis-
tics that reflect the performance/health of the three
channels of the Framer IC/system.
FEATURES
• Transmits, Receives and Processes data in the
• 3 Channel HDLC Controller - Tx and Rx
• Interfaces to all Popular Microprocessors
• Integrated Framer Performance Monitor
• Available in a 272 Ball PBGA package
• 3.3V Power Supply, 5V Tolerant I/O
• Operating Temperature -40°C to +85°C
APPLICATIONS
• Network Interface Units
• CSU/DSU Equipment.
• PCM Test Equipment
• Fiber Optic Terminals
• DS3/E3 Frame Relay Equipment
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
Controller
transmit
Receive
Interrupt
Output
T3/E3
T3/E3
Input
FAX (510) 668-7017
controller
controller
Interface
HDLC
HDLC
uP
XRT72L53
TxOHInd[n:0]
TxNibFrame[n:0]
TxFrame[n:0]
TxNibClk[n:0]
TxLnClk[n:0]
TxFrameRef[n:0]
TxNib[n:0]
TxSer[n:0]
A(11:0)
D(7:0)
ALE_AS
WR_R/W
CS
RDY_DTCK
Reset
INT
MOTO
RD_DS
RxClk[n:0]
RxOHind[n:0]
RxFrame[n:0]
RxNib[n:0]
RxSer[n:0]
RxOUTClk[n:0]
www.exar.com
REV. P1.1.8

Related parts for XRT72L53ES-75L03D-PCI

XRT72L53ES-75L03D-PCI Summary of contents

Page 1

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER MAY 2001 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is de- signed to accept User Data from the Terminal Equip- ment and insert this data into the Payload bit-fields within ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 XRT72L53 IGURE THE (See pin list for pin names and function ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTIONS PIN DESCRIPTION ONNECTION AME J18 NC ***** L19 NC ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME A1 TxLev[1] A2 EncoDis[1] A3 RxOOF[0] A4 RxRed[1] A5 REQ[0] A6 LLOOP[1] A7 RLOOP[1] A8 ExtLOS[1] A9 RxOHClk[1]/ RxHDLCClk[1] A10 TxOHClk[1] A11 TxOHFrame[1]/ TxHDLCClk[1] A12 TxOH[1]/ TxHDLCDat5[1] ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME A13 RxOHFrame[0]/ RxHDLCDat4[0] A14 TxOHClk[0] A15 TxOH[0]/ TxHDLCDat5[0] INS T YPE O Receive Overhead Frame Boundary Indicator/Receive ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME A16 TxNib2[1]/ TxHDLCDat2[1] A17 RxSer[1]/ RxIdle[1] A18 TxOHInd[1]/ TxHDLCDat6[1] A19 RxOHInd[1] A20 RxClk[1] B1 TDI B2 EncoDis[0] B3 RxLOS[1] B4 RxAIS[1] B5 RxRed[0] THREE CHANNEL DS3/E3 FRAMER ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME B6 Req[1] B7 RLOOP[0] B8 RLOL[0] B9 DMO[1] B10 RxOH[1]/ RxHDLCDat6[1] B11 TxOHIns[1]/ TxHDLCDat4[1] B12 TxAISEn[1] INS ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME B13 RxOHEnable[0]/ RxHDLCDat5[0] B14 TxOHEnable[0]/ TxHDLCDat7[0] B15 TxAISEn[0] B16 TxNib3[1]/ TxHDLCDat3[1] THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE O Receive Overhead Enable Indicator/Receive ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME B17 TxNibFrame[1]/ ValFCS[1] B18 RxFrame[1] B19 RxNib0[1]/ RxHDLCDat0[1] B20 RxNib2[1]/ RxHDLCDat2[1] C1 TxPOS[0] C2 TCK INS T ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME C3 TxLev[0] C4 RxLOS[0] C5 RxAIS[0] THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE O Transmit Line Build-Out Enable/Disable Select Output - Channel 0 ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME C6 TAOS[0] C7 LLOOP[0] C8 RLOL[1] C9 DMO[0] C10 RxOHFrame[1]/ RxHDLCDat4[1] C11 TxOHEnable[1]/ TxHDLCDat7[1] INS T YPE ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME C12 RxOH[0]/ RxHDLCDat6[0] C13 TxOHFrame[0]/ TxHDLCClk[0] THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE O Receive Overhead Data Output/Receive HDLC Data Output - Bit ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME C14 TxOHIns[0]/ TxHDLCDat4[0] C15 TxNib1[1]/ TxHDLCDat1[1] C16 TxSer[1]/ SndMsg[1] C17 TxFrame[1] C18 RxNib1[1]/ RxHDLCDat[1] C19 RxNib3[1]/ RxHDLCDat3[1] ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME C20 TxNib2[0]/ TxHDLCDat2[0] D1 TxNEG[0] D2 TRST D3 TMS D4 GND D5 RxOOF[1] D6 VDD D7 TAOS[1] D8 GND THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME D9 ExtLOS[0] D10 RxOHEnable[1]/ RxHDLCDat5[1] D11 VDD D12 RxOHClk[0]/ RxHDLCClk[0] D13 GND D14 TxNib0[1]/ TxHDLCDat0[1] D15 VDD ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME D18 TxNib0[0]/ TxHDLCDat0[0] D19 TxNib3[0]/ TxHDLCDat3[0] THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE I Transmit Nibble-Parallel Payload Data Input - Bit 0/Transmit HDLC ...

Page 17

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME D20 RxClk[0] E1 TxFrameRef[0] E2 TxLineClk[0] INS T YPE O Receive Clock Output Signal for Serial and ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME E3 RxOutClk[0]/ RxHDLCDat7[0] E4 TDO E17 TxNib1[0]/ TxHDLCDat1[0] THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE O Receive Out Clock - Transmit Payload Data ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME E18 TxSer[0]/ SndMsg[0] E19 TxOHInd[0]/ TxHDLCDat6[0] E20 TxFrame[0] INS T YPE I Transmit Serial Payload Data Input ...

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PRELIMINARY PIN DESCRIPTION C P ONNECTED AME F1 RxLineClk[0] F2 RxPOS[0] F3 RxNEG[0] F4 VDD F17 VDD THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE I Receiver LIU (Recovered) Clock Input ...

Page 21

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME F18 TxNIBClk[0]/ SndFCS[0] F19 RxSer[0]/ RxIdle[0] INS T YPE O Transmit Nibble Clock Output Signal/Transmit HDLC - ...

Page 22

PRELIMINARY PIN DESCRIPTION C P ONNECTED AME F20 RxFrame[0] G1 TxInClk[1] G2 RxNEG[1] G3 TxFrameRef[1] G4 TxInClk[0] THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE O Receive Boundary of DS3 or ...

Page 23

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME G17 TxNibFrame[0]/ ValFCS[0] G18 RxOHInd[0] INS T YPE O Transmit Frame Boundary Indicator - Nibble-Parallel Interface/ Transmit ...

Page 24

PRELIMINARY PIN DESCRIPTION C P ONNECTED AME G19 RxNib0[0]/ RxHDLCDat0[0] G20 RxNib1[0]/ RxHDLCDat1[0] H1 TxLineClk[1] H2 RxLineClk[1] H3 RxPOS[1] H4 GND H17 GND THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER INS T YPE ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME H18 RxNib2[0]/ RxHDLCDat2[0] H19 RxNib3[0]/ RxHDLCDat3[0] H20 Int J1 TxFrameRef[2] INS T YPE O Receive Nibble Output ...

Page 26

PRELIMINARY PIN DESCRIPTION C P ONNECTED AME J2 RxOutClk[1]/ RxHDLCDat7[1] J3 TxNEG[1] J4 TxPOS[1] J9 GND J10 GND J11 GND J12 GND J17 Rdy_Dtck J19 D[7] J20 D[6] K3 RxNEG[2] K4 VDD K9 GND ...

Page 27

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME K18 D[4] K19 D[3] K20 D[2] L1 TxInClk[2] L3 RxPOS[2] L9 GND L10 GND L11 GND L12 ...

Page 28

PRELIMINARY PIN DESCRIPTION C P ONNECTED AME N1 TxNEG[2] N3 TxLineClk[2] N4 GND N17 GND N18 A[4] N19 A[5] N20 A[6] P2 RxOutClk[2]/ RxHDLCDat7[2] P3 DMO[2] P17 WR_RW P18 A[1] P19 A[2] P20 A[3] ...

Page 29

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME R18 CS R19 ALE_AS R20 A[0] T1 RLOL[2] T3 RxOOF[2] T17 RxClk[2] T18 NibbleIntf T19 Reset INS ...

Page 30

PRELIMINARY PIN DESCRIPTION C P ONNECTED AME T20 MOTO U3 RxAIS[2] U4 GND U5 RLOOP[2] U6 VDD U8 GND U9 RxOHEnable[2]/ RxHDLCDat5[2] U10 VDD U11 TxSer[2]/ SndMsg[2] U12 TxNib2[2]/ TxHDLCDat2[2] U13 GND U14 TxFrame[2] ...

Page 31

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 PIN DESCRIPTION C P ONNECTED AME V7 TxOH[2]/ TxHDLCDat5[2] V16 RxNib3[2]/ RxHDLCDat3[2] V17 RxNib1[2]/ RxHDLCDat1[2] V20 Rd_DS W1 LLOOP[2] W2 TAOS[2] W3 RxRed[2] ...

Page 32

PRELIMINARY PIN DESCRIPTION C P ONNECTED AME W11 TxOHFrame[2]/ TxHDLCClk[2] W12 TxNib3[2]/ TxHDLCDat3[2] W13 TxNib1[2]/ TxHDLCDat1[2] W15 TxNIBClk[2]/ SndFCS[2] W16 TxNibFrame[2]/ ValFCS[2] W19 RxSer[2]/ RxIdle[2] W20 RxOHInd[2] Y4 EncoDis[2] Y7 RxOH[2]/ RxHDLCDat6[2] Y10 TxOHEnable[2]/ ...

Page 33

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.8 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUMS Power Supply......................................... -0.3V to +3.6V Storage Temperature ...............................-55°C to 150°C voltage at Any Pin .......................... -0.3V to VDD + 0.3V DC ELECTRICAL CHARACTERISTICS Test Conditions: ...

Page 34

PRELIMINARY AC ELECTRICAL CHARACTERISTICS Test Conditions 25°C, VDD = 3. unless otherwise specified S P YMBOL ARAMETER t TxInClk to TxFrame output delay 10 Transmit Payload Data Input Interface - Looped-Timed/Nibble Mode (See Figure 5) t ...

Page 35

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.8 AC ELECTRICAL CHARACTERISTICS (CONT.) Test Conditions 25°C, VDD = 3. unless otherwise specified S P YMBOL ARAMETER Transmit Overhead Input Interface Timing - Method 1 ...

Page 36

PRELIMINARY AC ELECTRICAL CHARACTERISTICS (CONT.) Test Conditions 25°C, VDD = 3. unless otherwise specified S P YMBOL ARAMETER t TxInClk clock (falling) edge to TxOHIns hold-time 27 t TXOHIns to TxInClk (falling edge) set-up Time 28 ...

Page 37

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.8 AC ELECTRICAL CHARACTERISTICS (CONT.) Test Conditions 25°C, VDD = 3. unless otherwise specified S P YMBOL ARAMETER t RxPOS or RxNEG set-up time to falling ...

Page 38

PRELIMINARY AC ELECTRICAL CHARACTERISTICS (CONT.) Test Conditions 25°C, VDD = 3. unless otherwise specified S P YMBOL ARAMETER Microprocessor Interface - Intel (See Figure 17) t A10 - A0 Setup Time to ALE_AS Low 64 t ...

Page 39

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.8 1.0 TIMING DIAGRAMS IGURE IMING IAGRAM FOR RANSMIT DS3 L -T ING IN BOTH THE AND OOP XRT72L5x Transmit Payload Data I/F Signals RxOutClk ...

Page 40

PRELIMINARY IGURE IMING IAGRAM FOR THE DS3/N IS OPERATING IN BOTH THE IBBLE AND t13A RxOutClk TxNibClk TxNib[3:0] TxNibFrame t13 IGURE IMING IAGRAM FOR THE DS3/N IS OPERATING IN THE IBBLE AND ...

Page 41

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE IMING IAGRAM FOR THE t22 t23 t21 TxOHClk TxOHFrame TxOHIns X bit = 0 TxOH t24 t25 IGURE IMING IAGRAM ...

Page 42

PRELIMINARY LIU I IGURE RANSMIT NTERFACE " " THE RISING EDGE OF X INE LK t32 TxLineClk t30 TxPOS TxNEG F 10. T LIU I IGURE RANSMIT NTERFACE " THE FALLING EDGE OF ...

Page 43

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.8 F 11. R LIU I IGURE ECEIVE NTERFACE " " THE RISING EDGE OF X INE LK RxLineClk t40 RxPOS RxNEG F 12. R LIU I IGURE ...

Page 44

PRELIMINARY F 13 IGURE ECEIVE AYLOAD ATA XRT72L5x Receive Payload Data I/F Signals RxClk RxSer Payload[4702] RxFrame RxOHInd F 14 IGURE ECEIVE AYLOAD ATA XRT72L5x Receive Payload Data I/F Signals RxOutClk RxClk RxNib[3:0] RxFrame ...

Page 45

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE ECEIVE VERHEAD RxOHClk RxOHFrame RxOH t59B F 16 IGURE ECEIVE VERHEAD t60 RxOutClk RxOHEnable RxOHFrame RxOH UDL ...

Page 46

PRELIMINARY F 17 IGURE ICROPROCESSOR NTERFACE t64 ALE_AS A[10:0] CS D[7:0] RD_DS WR_R/W RDY_DTCK F 18 IGURE ICROPROCESSOR NTERFACE t64 ALE_AS A[10:0] t770 CS D[7:0] RD_DS WR_R/W THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER T ...

Page 47

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE ICROPROCESSOR NTERFACE ALE_AS A[10:0] CS D[7:0] Not Valid Valid Data at Offset =0x01 RD_DS WR_R/W RDY_DTCK 20 IGURE ICROPROCESSOR ...

Page 48

PRELIMINARY F 21 IGURE ICROPROCESSOR NTERFACE t 78 ALE_AS A(10:0) CS D(7:0) RD_DS WR_R/W RDY_DTCK F 22 IGURE ICROPROCESSOR NTERFACE t 78 ALE_AS A(10:0) CS D(7:0) RD_DS WR_R/W RDY_DTCK THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC ...

Page 49

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE ICROPROCESSOR NTERFACE Reset IMING ESET ULSE IDTH t90 49 PRELIMINARY ...

Page 50

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.0 THE MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports com- munication between the local microprocessor (µP) and the Framer IC. In particular, the Microprocessor Interface section supports the following operations ...

Page 51

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE IMPLE LOCK IAGRAM OF THE A(10:0) WR_R/W Rd_DS ALE_AS Reset D[7:0] MOTO RDY_DTCK 2 ICROPROCESSOR NTERFACE NAL The Framer ...

Page 52

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY ABLE ESCRIPTION OF THE AME YPE MOTO I Selection input for Intel/Motorola µP Interface. Setting this pin to a logic "High" configures the ...

Page 53

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 ABLE IN ESCRIPTION OF THE I NTERFACE IS OPERATING IN THE E P QUIVALENT AME IN OTOROLA YPE ENVIRONMENT ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY Byte). When an 8-bit PMON Register is concatenated with its companion 8-bit PMON Register, one obtains the full 16-bit expression within that PMON Register. The consequence of having these 16-bit registers ...

Page 55

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 RD_DS (Read Strobe) input pin "Low". This action also enables the bi-directional data bus output drivers of the Framer. At this point, the bi- directional data bus output drivers ...

Page 56

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY the µC/µP should toggle the WR_R/W Strobe) input pin "High". This action accom- plishes two things latches the contents of the bi-directional data bus into the XRT72L53 DS3/E3 Framer ...

Page 57

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 nate the Read Cycle by toggling the RD_DS (Data Strobe) input pin "High". Figure 27 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals F ...

Page 58

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 28 IGURE LLUSTRATION OF THE P I TYPE ROGRAMMED RITE PERATION ALE_AS A(10:0) CS D(7:0) RD_DS WR_R/W RDY_DTCK 2.3.2.2 Data Access using Burst Mode I/O Burst ...

Page 59

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 A.2 While the µC/µP is placing this address value onto the Address Bus, the Address Decoding circuitry (within the user's system) should assert the CS input pin of the ...

Page 60

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY B.0 Execute each subsequent Read Cycles, as described in steps 1 through 3 below. B.1 Without toggling the ALE_AS input pin (e.g., keeping it "Low"), toggle the RD_DS input pin "Low". ...

Page 61

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Each of these operations within the burst access are described below. 2.3.2.2.1.2.1 The Initial Write Operation The initial write operation of an Intel-type Write Burst Access is accomplished by ...

Page 62

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The procedure that the µC/µP must use to perform the remaining write cycles, within this burst access operation, is presented below. B.0 Execute each subsequent write cycle, as described in steps ...

Page 63

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 A.0 Execute a Single Ordinary (Programmed I/ O) Read Cycle, as described in steps A.1 through A.8 below. A.1 Assert the ALE_AS (AS*) input pin by toggling it "Low". ...

Page 64

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The procedure that the µC/µP must use to perform the remaining read cycles, within this Burst Access operation, is presented below. B.0 Execute each subsequent Read Cycle, as described in steps ...

Page 65

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 A.0 Execute a Single Ordinary (Programmed I/ O) Write cycle, as described in Steps A.1 through A.7 below. A.1 Assert the ALE_AS (Address Strobe) input pin by toggling it ...

Page 66

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.3.2.2.2.2.2 The Subsequent Write Operations The procedure that the µC/µP must use to perform the remaining write cycles, within this burst access operation, is presented below. B.0 Execute each subsequent write ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 RUR - Reset-upon-Read Registers Additionally, some of these registers consists of both R/O and R/W bit-fields. These registers are denoted in Table 5 as Combination of R/W and R/O. ...

Page 68

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY ABLE EGISTER A R DDRESS EGISTER 0x1C RxE3 TTB-0 Register - G.832 0x1D RxE3 TTB-1 Register - G.832 0x1E RxE3 TTB-2 Register - G.832 0x1F RxE3 TTB-3 Register ...

Page 69

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 ABLE EGISTER A R DDRESS EGISTER 0x39 TxDS3 F-Bit Mask Register 4 TxE3 TTB-1 Register - G.832 0x3A TxE3 TTB-2 Register - G.832 0x3B TxE3 TTB-3 ...

Page 70

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY ABLE EGISTER A R DDRESS EGISTER 0x5A - 0x67 Reserved 0x68 PRBS Bit Error Counter - MSB 0x69 PRBS Bit Error Counter - LSB 0x6A-0x6B Reserved 0x6C PMON ...

Page 71

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Bit 7 - Local Loopback Mode This Read/Write bit-field is used to command the Framer chip to operate in the Local Loopback Mode. Setting this bit-field to "0", configures ...

Page 72

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.4.2.2 I/O Control Register I/O CONTROL REGISTER (ADDRESS = 0X01 Disable LOC Disable TxLOC RxLOC R Bit 7 - Disable ...

Page 73

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Setting this bit-field to "1" configures the XRT72L53 to output data, via the TxPOS and TxNEG output pins, on the falling edge of TxLineClk. Bit 1 - RxLineClk Invert ...

Page 74

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY this bit-field to "0" does disable all Receive Section related Interrupts. Bit 1 - TxDS3/E3 Interrupt Enable This Read/Write bit-field is used to enable or disable all Transmit Section related interrupts ...

Page 75

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Bit 7 - TxOH Source Select This Read/Write bit-field is used to configure the Transmit Section of the channel to accept overhead bits/bytes via the TxSer[n] or TxNib[3:0][n] input ...

Page 76

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10 RxAIS RxLOS RxIdle Bit 7 - RxAIS (Receive AIS Pattern) Indicator ...

Page 77

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Receive DS3/E3 Framer block will declare an Out of Frame (OOF) condition is 6 out of 16 F-bits are in er- ror For more information on the ...

Page 78

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY This Read/Write bit-field is used to enable or disable the Detection of CP-Bit Error Interrupt. Setting this bit-field to “1’ enables this interrupt. Setting this bit- field to “0” disables this ...

Page 79

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 ister was read. This bit-field will be asserted under ei- ther of the following conditions: For DS3 Applications 1. When the Receive DS3/E3 Framer block detects the occurrence of ...

Page 80

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY Bit 0 - P-Bit Error Interrupt Status This Reset Upon Read bit-field indicates whether or not the Detection of P-bit error interrupt has occurred since the last read of this register. ...

Page 81

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 ceive DS3/E3 Framer block. This bit is cleared to "0" when the FEAC code is removed For more information on the role of this bit-field and OTE ...

Page 82

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY indicates that the LAPD Message Reception Com- plete interrupt has occurred since the last read of this register. RXDS3 LAPD STATUS REGISTER (ADDRESS = 0X19 ...

Page 83

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 RXE3 CONFIGURATION & STATUS REGISTER 1 (ADDRESS = 0X10 RxPLDType[2: Bit RxPLDType[2:0] (Received ...

Page 84

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.4.3.2 Receive E3 Configuration & Status Register 2 (E3, ITU-T G.832) RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11 LOF Algo RxLOF ...

Page 85

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 consecutive E3 frames, with the FERF bit-field (within the MA byte) set to "1". This user-selectable number is either frames. Conversely, the Receive E3 Framer ...

Page 86

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.4.3.4 3.3.2.18 Receive E3 Interrupt Enable Register - 2 (E3, ITU-T G.832) RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13 Not Used TTB ...

Page 87

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Bit 6 - SSM Message Interrupt Status This Reset-upon-Read bit-field indicates whether or not a Change of Synchronization Status Message (SSM) Interrupt has occurred since the last read of ...

Page 88

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The local µP can determine the current state of the AIS condition by reading bit 7 of the Rx E3 Configura- tion and Status Register (Address = 0x11 For ...

Page 89

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 2.4.3.7 Receive E3 LAPD Control Register (E3, ITU-T G.832) RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 Not Used ...

Page 90

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY table relates the contents of these bit-fields to the LAPD Message type/size. R LAPDT [1:0] X YPE Bit Type This Read-Only bit-field indicates ...

Page 91

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read-Only register contains the value of the GC byte, residing in the most recently received E3 frame. Please see Section 5.3.3 for a more detailed discus- sion on ...

Page 92

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.4.3.14 Receive E3 TTB-3 Register (E3, ITU-T G.832) RXE3 TTB-3 REGISTER (ADDRESS = 0X1F This Read-Only register contains the ...

Page 93

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read-Only register contains the seventh (7th) byte within the 16 byte Trail Trace Buffer Message, that has been received from the Remote Terminal. This register typical contains an ...

Page 94

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.4.3.21 Receive E3 TTB-10 Register (E3, ITU-T G.832) RXE3 TTB-10 REGISTER (ADDRESS = 0X26 This Read-Only register contains the ...

Page 95

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read-Only register contains the fourteenth (14th) byte within the 16 byte Trail Trace Buffer Mes- sage, that has been received from the Remote Termi- nal. This register typical ...

Page 96

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY October 1998 Revision of the ITU-T G.832 Framing format for E3. Bits 3-0 - RxSSM[3:0] - Received Synchronization Status Message These four Read-Only bits reflect the content of the SSM, which ...

Page 97

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 For more information on the LOF and OOF condi- OTE tion, please see Section 4.3.2.2. Bit 6 - RxLOF (Receive Loss of Frame) Status This Read-Only bit-field ...

Page 98

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY This Read/Write bit-field allows the user to enable or disable the Change in LOS condition interrupt. Set- ting this bit-field to "1" enables this interrupt. Setting this bit-field to "0" disables ...

Page 99

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 1. When the Receive DS3/E3 Framer block has detected the appropriate conditions to declare an OOF Condition. 2. When the Receive DS3/E3 Framer block has transitioned from the OOF ...

Page 100

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2. When the Receive DS3/E3 Framer block detects the end of the Rx FERF Condition (e.g., when the FERF bit, within the last consecutive E3 frames are set ...

Page 101

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read-Only bit-field indicates whether or not the LAPD Receiver is currently detecting an abort se- quence (e.g., a string of 7 consecutive "1’s"). This bit-field is set to ...

Page 102

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY TRANSMIT DS3 CONFIGURATION REGISTER (ADDRESS = 0X30 Yellow Tx X Bits Tx Idle Alarm R/W R/W R Bit ...

Page 103

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Writing a '1' to this bit-field invokes this command, causing the Transmit DS3/E3 Framer block to gener- ate an all '0' pattern For more information on this ...

Page 104

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY • Serially transmit this 16-bit FEAC Message to the far-end receiver via the outbound DS3 data-stream, 10 consecutive times For more information on the Transmit FEAC Proces- OTE sor, ...

Page 105

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 For information on the LAPD Transmitter, please see OTE Section 3.2.3.2. TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34 ...

Page 106

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY Bit TxFEBEDat[2:0] These three (3) read/write bit-fields, along with Bit 4 of this register, allows the user to configure and trans- mit his/her choice for the three (3) ...

Page 107

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 TXDS3 F-BIT MASK REGISTER - 2 (ADDRESS = 0X37 FBit Mask[23] FBit Mask[22] FBit Mask[21] FBit Mask[20] FBit Mask[19] FBit Mask[18] FBit ...

Page 108

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 2.4.6.1 Transmit E3 Configuration Register (E3, ITU-T G.832) TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30 Not Used Bit 4 - ...

Page 109

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 been written into Bit 6 (FEBE) within the Tx MA Byte register, will be the value of the FEBE bit-field, in the outbound E3 frame. Writing a "1" into ...

Page 110

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY • Read in this stuffed PMDL Message from the Trans- mit LAPD Message buffer, and encapsulate it into a LAPD Message frame. • Fragment the resulting LAPD Message frame into octets. ...

Page 111

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read/Write byte-fields is used to specify the contents of the MA byte-field in each outbound E3 frame The values written into bit-fields 6 (FEBE) and 7 ...

Page 112

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY mitting Terminal. The Transmit DS3/E3 Framer block will take the contents of these 16 registers, and insert them into the TR byte of the outbound E3 frame. In the first of ...

Page 113

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 TXE3 TTB-3 REGISTER (ADDRESS = 0X3B R/W R/W R This Read/Write byte-field, along with the TxTTB-0 through TxTTB-2 and TxTTB-4 ...

Page 114

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY the TR byte-field, within the very next outbound E3 frame. The contents of this register, along with Tx TTB-1 through Tx TTB-4 and Tx TTB-6 through Tx TTB-15 TXE3 TTB-6 REGISTER ...

Page 115

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read/Write byte-field, along with the Tx TTB-0 through Tx TTB-7 and Tx TTB-9 through Tx TTB-15 registers permit a user to define a Trail Access Point Identifier sequence ...

Page 116

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY TXE3 TTB-11 REGISTER (ADDRESS = 0X43 R/W R/W R This Read/Write byte-field, along with the Tx TTB-0 through Tx TTB-10 and Tx ...

Page 117

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 Frames, the Transmit DS3/E3 Framer block will read in the contents of this register, and insert it into the TR byte-field, within the very next outbound E3 ...

Page 118

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY This Read/Write bit-field is used to insert errors into the Framing Alignment octet, FA1 of each outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior ...

Page 119

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read/Write bit-field is used to configure the Transmit Section of the Channel, to compute an insert the BIP-4 value into each outbound E3 frame. Setting this bit-field to ...

Page 120

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY a. Internally generate the FAS (Framing Alignment Signal) pattern, within the outbound E3 frames use the Input Interface as the source for the FAS pattern. Setting this bit-field ...

Page 121

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 data, immediately following any string of 5 consecu- tive "1’s". • Read in this stuffed PMDL Message from the Trans- mit LAPD Message buffer, and encapsulate it into a ...

Page 122

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY FAS of each outbound E3 frame. The user may wish to do this for equipment testing purposes. Prior to transmission, the Transmit E3 Framer block reads in the upper five (5) ...

Page 123

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x51) contains a 16-bit representation of the number of Line Code Violations that have ...

Page 124

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54 RUR RUR RUR 0 0 This Reset-upon-Read register, along with the PMON Parity Error ...

Page 125

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Reset-upon-Read register, along with the PMON FEBE Event Count Register - MSB (Address = 0x56) contains a 16-bit representation of the number of FEBE Events that have been ...

Page 126

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY Hence, the contents of the other byte (of the partially read PMON register) will reside within the PMON Holding register. ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D ...

Page 127

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70 This Read-Only register, along with ...

Page 128

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY This Read-Only register, along with the Frame CP-Bit Error - One-Second Accumulator Register - LSB (Ad- dress = 0x73) contains a 16-bit representation of the number of CP Bit Errors that ...

Page 129

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 ENCODIS or the ENDECDIS input pin of the DS3/E3 LIU IC. If the user forces this signal to toggle "High", then the internal B3ZS/HDB3 encoder (within the LIU) will ...

Page 130

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY the customer is not using an Exar XRT73L0X OTE DS3/E3/STS-1 LIU IC, then this bit-field and the RLOOP[n] output pin can be used for other purposes. Bit 0 ...

Page 131

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Conversely, if this bit-field contains a logic “0”, then the RLOL input pin is "Low". The DS3/E3 LIU IC will hold this pin "Low" as long as this clock ...

Page 132

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY Setting this bit-field to “0” configures the Transmit HDLC Controller block to compute and append the CRC-16 value to the end of the outbound HDLC frame. Further, this setting also configures ...

Page 133

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 stant location in system memory, the PMON Holding Register. 2 NTERRUPT TRUCTURE WITHIN THE M I ICROPROCESSOR NTERFACE The XRT72L53 Framer is equipped with a ...

Page 134

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY XRT72L53 F ABLE ISTING OF THE A L DDRESS OCATION Block Interrupt Enable Register Block Interrupt Status Register ...

Page 135

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05 RxDS3/E3 Interrupt Status The Block Interrupt Status Register presents the ...

Page 136

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY T 10: I ABLE NTERRUPT NTERRUPTING HE EXT F B UNCTIONAL LOCK Receive Section RxDS3 Interrupt Status Register RxDS3 FEAC Interrupt Enable/Status Register RxDS3 LAPD Control Register Transmit ...

Page 137

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 non quickly results in the local Microprocessor/Micro- controller being tied continuous cycle of exe- cuting this one interrupt service routine. Consequent- ly, the local Microprocessor/Microcontroller (along ...

Page 138

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The remaining registers, listed in Table 10, Table 11 and Table 12 will be presented in the discussion of the functional blocks, within the XRT72L53 Framer IC. These discussions will present ...

Page 139

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 8051 Microcontroller IC and cannot be changed. Table 14 presents the location (in code memory ABLE NTERRUPT ERVICE I NTERRUPT PIN INT0* INT1* Therefore, ...

Page 140

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY and will then branch program control to the Framer in- terrupt service routine. In the case of Figure 37, the interrupt service routine will be located in 0x0003 in code memory. ...

Page 141

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 (U4) to also toggle "Low”. In response to this, the In- terrupt Priority Encoder chip will set its three outputs to the following states ‘0’ ...

Page 142

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY control over many aspects of the XRT7300 DS3/E3/ STS-1 LIU IC without having to develop the neces- sary off-chip glue-logic IGURE CHEMATIC EPICTING HOW TO INTERFACE THE ...

Page 143

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 neClk[n] signals will be routed directly to the Tx- POS[n], TxNEG[n] and TxLineClk[n] signals. Setting this bit-field to “1” configures the channel to operate in the Remote Loop-Back Mode. ...

Page 144

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY the customer is not using the XRT7300 DS3/E3/ OTE STS-1 IC, then this bit-field and the TxLEV output pin can be used for other purposes. Bit 1 - ...

Page 145

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 This Read-Only bit-field indicates the logic state of the DMO output pin of the Framer. This input pin is in- tended to be connected to the DMO output pin ...

Page 146

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY XRT72L53 CONFIGURATION The XRT72L53 DS3/E3 Framer IC can be configured to support any of the following four framing formats. • DS3/C-Bit Parity • DS3/M13 • E3/ITU-T G.832 • E3/ITU-T G.751 As ...

Page 147

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 F 40. DS3 F F IGURE RAME ORMAT FOR FEBE UDL ...

Page 148

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00 Table 17 lists the relationship between the value of the this bit-field and ...

Page 149

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 DS3 terminals. Therefore, each DS3 M-frame con- sists of a total of 28 F-bits. These F-bits exhibit a re- peating pattern of "1001" within each F-frame. This fact is ...

Page 150

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The third C-bit (C13 or FEAC) in the first F-frame is used as the Far End Alarm and Control (FEAC) chan- nel between the Near-End DS3 terminal and the Re- mote ...

Page 151

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE IMPLE LLUSTRATION OF THE DS3 M FIGURED TO OPERATE IN THE TxOHFrame TxOHEnable Transmit Overhead TxOH Input TxOHClk Interface Block TxOHIns TxOHInd TxSer ...

Page 152

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 43 IGURE IMPLE LLUSTRATION OF THE TxOH_Ind TxSer TxNib[3:0] TxInClk TxNibClk TxFrame TxFrameRef Each of the input and output pins of the Transmit Pay- load Data Input ...

Page 153

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 ABLE ISTING AND ESCRIPTION OF THE PINS ASSOCIATED WITH THE IGNAL AME YPE TxSer Input Transmit Serial Payload Data Input Pin: If ...

Page 154

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY T 19 ABLE ISTING AND ESCRIPTION OF THE PINS ASSOCIATED WITH THE IGNAL AME YPE TxFrameRef Input Transmit Frame Reference Input: The XRT72L53 permits the user ...

Page 155

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Figure 44 presents an illustration of the Transmit Pay- load Data Input Interface block (within the XRT72L53) F 44. I IGURE LLUSTRATION OF THE XRT72L53) NPUT ...

Page 156

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY . F 45 IGURE EHAVIOR OF THE ERMINAL I XRT72L53 NTERFACE BLOCK OF THE Terminal Equipment Signals DS3_Clock_In DS3_Data_Out Tx_Start_of_Frame DS3_Overhead_Ind XRT72L5x Transmit Payload Data I/F Signals RxOutClk TxSer ...

Page 157

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 A. Local-Timing - Uses the TxInClk signal as the Timing Reference In this mode, the Transmit Section of the XRT72L53 will use the TxInClk signal as its timing reference. ...

Page 158

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY N : OTES 1. In this case, the Terminal Equipment is controlling the start of Frame Generation, and is therefore referred to as the Frame Master. Conversely, since the XRT72L53 does ...

Page 159

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00 Interface the XRT72L53, to the Terminal Equip- ment, as illustrated in Figure ...

Page 160

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY rising edge of the signal at the DS3_Clock_In input pin. Similarly, the XRT72L53 will latch the data, resid- ing on the TxSer input pin, on the rising edge of TxIn- Clk. ...

Page 161

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00 Local Loopback DS3/E3* Internal LOS Enable R/W R/W R Interface ...

Page 162

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 50. I IGURE LLUSTRATION OF THE I I XRT72L53 NPUT NTERFACE BLOCK OF THE DS3_Nib_Clock_In DS3_Data_Out[3:0 ] Tx_Start_of_Fram Terminal Mode 4 Operation of the Terminal Equipment When the XRT72L53 is ...

Page 163

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 IGURE EHAVIOR OF THE ERMINAL QUIPMENT ODE PERATION Terminal Equipment Signals RxOutClk DS3_Nib_Clock_In DS3_Data_Out[3:0] Tx_Start_of_Frame XRT72L5x Transmit Payload Data I/F ...

Page 164

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY 4.2.1.5 Mode 5 - The Nibble-Parallel/Local- Timed/Frame-Slave Interface Mode Behavior of the XRT72L53 If the XRT72L53 has been configured to operate in this mode, then the XRT72L53 will function as fol- ...

Page 165

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 F 52. I IGURE LLUSTRATION OF THE I I XRT72L53 NPUT NTERFACE BLOCK OF THE ATION DS3_Nib_Clock_In DS3_Data_Out[3:0] Tx_Start_of_Frame Terminal Equipment Mode 5 Operation of the Terminal Equipment In ...

Page 166

THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 53 IGURE EHAVIOR OF THE ERMINAL E (DS3 QUIPMENT ODE PERATION Terminal Equipment Signals TxInClk DS3_Nib_Clock_In DS3_Data_Out[3:0] Nibble [1175] Tx_Start_of_Frame XRT72L5x Transmit Payload Data I/F ...

Page 167

XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 TxNibClk signal, to latch the data, residing on the Tx- Nib[3:0] into its circuitry. B. Nibble-Parallel Mode The XRT72L53 will accept the DS3 payload data, from the Terminal Equipment, ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY the 11.184MHz clock signal via the DS3_Nib_Clock_In input pin. The XRT72L53 will out- put the 11.184MHz clock signal via the TxNibClk out- put pin. The Terminal Equipment will serially output the ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00 Local Loopback DS3/E3* Internal LOS Enable R/W R/W R Interface ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The Performance Monitoring Overhead Bits (P and CP Bits) The P-bits are always internally generated by the Transmit Section of the XRT72L53. The “P” bits are used by the Remote Terminal ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 The Transmit Overhead Data Input Interface consists of the five signals. Of these five (5) signals, the fol- lowing four (4) signals are to be used when imple- menting ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 57. I IGURE LLUSTRATION OF THE NPUT NTERFACE ETHOD DS3_OH_Clock_In DS3_OH_Out] Tx_Start_of_Frame Insert_OH Terminal Equipment Method 1 Operation of the Terminal Equipment If the Terminal Equipment ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 ABLE HE ELATIONSHIP BETWEEN THE WAS LAST SAMPLED UMBER OF ISING LOCK DGES IN T OHC (Clock edge ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY T 22 ABLE HE ELATIONSHIP BETWEEN THE WAS LAST SAMPLED UMBER OF ISING LOCK DGES IN T OHC ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 F 58. I IGURE LLUSTRATION OF THE SIGNAL THAT MUST OCCUR BETWEEN THE XRT72L53, IN ORDER TO CONFIGURE THE EQUIPMENT Terminal Equipment/XRT72L5x Interface Signals 0 TxOHClk TxOHFrame TxOHIns TxOH ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY Method 1 requires the use of an additional clock sig- nal, TxOHClk. However, there may be a situation in which the user does not wish to accommodate and process this extra ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 F 59. I IGURE LLUSTRATION OF THE NPUT NTERFACE ETHOD DS3_Clock_In DS3_OH_Enable DS3_OH_Out Tx_Start_of_Frame Insert_OH Terminal Equipment Method 2 Operation of the Terminal Equipment If ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY T 24 ABLE HE ELATIONSHIP BETWEEN THE T OHF ) THE X RAME PULSE TO THE N T OHE P UMBER OF X NABLE ULSES 0 (The TxOHEnable and ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 ABLE HE ELATIONSHIP BETWEEN THE T OHF ) THE X RAME PULSE TO THE N T OHE P UMBER OF X NABLE ULSES 38 39 ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 60 IGURE EHAVIOR OF RANSMIT THE ERMINAL QUIPMENT FOR ETHOD TxInClk TxOHFrame TxOHEnable TxOHIns TxOH Terminal Equipment samples “TxOHFrame” and “TxOHEnable” being “HIGH” Terminal ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 1. Write the 6-bit FEAC code (to be sent) into the Tx DS3 FEAC Register. 2. Enable the Transmit FEAC Processor. 3. Initiate the Transmission of the FEAC Message. ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY all 1s in the FEAC bit-field of each DS3 Frame. The Receive FEAC Processor (at the remote terminal equipment) will interpret this all 1s message as an Idle FEAC Message. The ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 F 62. LAPD M F IGURE ESSAGE RAME Where: Flag Sequence = 0x7E SAPI + 0x3C or 0x3E TEI + EA = 0x01 Control = ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The 16 bit FCS (Frame Check Sequence) is calculat- ed over the LAPD Message Header and Information Payload bytes, by using the CRC-16 polynomial ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 Prior to executing step 2 (Enabling the LAPD Trans- mitter), the LAPD Transmitter will be disabled and the Transmit DS3 Framer block will be setting each of the DL ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY subsequent "0" from the payload portion of the incoming LAPD message. Figure 63 presents a flow chart depicting the proce- dure (in 'white boxes') that the user should use in or- ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00 Local Loop- DS3/E3* Internal back LOS Enable R/W R/W R This action will ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY If the user's local Data Link Equipment activates the Transmit Overhead Data Input Interface block and writes data into this interface for these bits, then the Transmit DS3 Framer block will ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 • Generate and transmit a desired value for FEBE (Far-End-Block Error). The procedure and results of generating any of these alarm conditions is presented below. TX DS3 CONFIGURATION REGISTER ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY T 30 ABLE HE ELATIONSHIP BETWEEN THE CONTENTS OF R EGISTER Normal Operation: The Overhead bits are either internally generated, or they are inserted via ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1 ABLE HE ELATIONSHIP BETWEEN THE CONTENTS EGISTER AND THE RESULTING Normal Operation: The Overhead bits are either internally ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY The bit-fields of the Tx DS3 M-bit Mask Register, that are relevant to error-insertion are shaded. The re- maining bit-fields pertain to the FEBE bit-fields, and are discussed in Section 4.2.4.2.1.9. ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 The XRT72L53 Framer digital device that takes DS3 payload and overhead bit information from some terminal equipment, processes this data and ul- timately, multiplexes this information ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 66 IGURE IMPLE LLUSTRATION OF THE From Transmit DS3 Framer Block The Transmit DS3 LIU Interface block can transmit data to the LIU IC or other external ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 TxLineClk output pins, for this mode are discussed below. TxPOS - Transmit Positive Polarity Pulse: The Transmit DS3 LIU Interface block will assert this out- put to the LIU ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 68. I AMI L IGURE LLUSTRATION ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 I/O CONTROL REGISTER (ADDRESS = 0X01 Disable TxLOC LOC Disable RxLOC R Table 34 relates the content of ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY F 70 IGURE AVEFORM IMING ELATIONSHIP BETWEEN ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF t32 TxLineClk t30 TxPOS TxNEG F 71 IGURE ...

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XRT72L53 THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.7 BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04 RxDS3/E3 Interrupt Enable R Setting this bit-field to “1” enables the ...

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THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER PRELIMINARY • Set Bit 3 (Tx FEAC Interrupt Status) within the Tx DS3 FEAC Configuration & Status Register, as illustrated below. TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) B ...

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