MAX11103EVKIT+ Maxim Integrated Products, MAX11103EVKIT+ Datasheet - Page 22

• Manufacturer Part Number: MAX11103EVKIT+
• Description: Power Management Modules & Development Tools MAX11103 EVAL KIT MAX11103 EVAL KIT
• Manufacturer: Maxim Integrated Products

Specifications of MAX11103EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
The MAX11102/MAX11103/MAX11105/MAX11106/MAX11110/
MAX11111/MAX11115/MAX11116/MAX11117 are fast,
12-/10-/8-bit, low-power, single-supply ADCs. The
devices operate from a 2.2V to 3.6V supply and con-
sume only 8.3mW (V DD = 3V)/5.2mW (V DD = 2.2V) at
3Msps and 6.2mW (V DD = 3V)/3.7mW (V DD = 2.2V) at
2Msps. The 3Msps devices are capable of sampling
at full rate when driven by a 48MHz clock and the
2Msps devices can sample at full rate when driven by
a 32MHz clock. The dual-channel devices provide a
separate digital supply input (OVDD) to power the digi-
tal interface enabling communication with 1.5V, 1.8V,
2.5V, or 3V digital systems.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit, 10-bit, or 8-bit result.
A 12-bit result is followed by two trailing zeros, a 10-bit
result is followed by four trailing zeros, and an 8-bit result
is followed by six trailing zeros. See Figures 1 and 5.
The dual-channel devices feature a dedicated refer-
ence input (REF). The input signal range for AIN1/AIN2
is defined as 0V to V
single-channel devices use V
input signal range of AIN is defined as 0V to V
respect to GND.
Figure 5. 10-/8-Bit Timing Diagrams
22
DOUT
DOUT
SCLK
SCLK
_____________________________________________________________________________________
CS
CS
IMPEDANCE
IMPEDANCE
16
16
HIGH
HIGH
1
1
0
0
Detailed Description
REF
2
2
D9
D7
with respect to AGND. The
DD
3
3
D8
D6
as the reference. The
4
4
D7
D5
5
5
D6
D4
6
6
DD
D5
D3
with
7
7
D4
D2
8
8
These ADCs include a power-down feature allowing
minimized power consumption at 2.5FA/ksps for lower
throughput rates. The wake-up and power-down feature
is controlled by using the SPI interface as described in
the Operating Modes section.
The devices feature a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE devices without
external logic. Figures 1 and 5 show the interface sig-
nals for a single conversion frame to achieve maximum
throughput.
The falling edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal
(SCLK) controls the conversion.
The SAR core successively extracts binary-weighted bits
in every clock cycle. The MSB appears on the data bus
during the 2nd clock cycle with a delay outlined in the
timing specifications. All extracted data bits appear suc-
cessively on the data bus with the LSB appearing during
the 13th/11th/9th clock cycle for 12-/10-/8-bit operation.
The serial data stream of conversion bits is preceded by
a leading “zero” and succeeded by trailing “zeros.” The
data output (DOUT) goes into high-impedance state dur-
ing the 16th clock cycle.
D3
D1
9
9
D2
D0
10
10
D1
0
11
11
D0
0
12
12
0
0
13
13
0
0
14
14
Serial Interface
0
0
15
15
IMPEDANCE
IMPEDANCE
0
0
16
16
HIGH
HIGH
1
1