MAX11103EVKIT+ Maxim Integrated Products, MAX11103EVKIT+ Datasheet - Page 23

• Manufacturer Part Number: MAX11103EVKIT+
• Description: Power Management Modules & Development Tools MAX11103 EVAL KIT MAX11103 EVAL KIT
• Manufacturer: Maxim Integrated Products

Specifications of MAX11103EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To sustain the maximum sample rate, all devices have to
be resampled immediately after the 16th clock cycle. For
lower sample rates, the CS falling edge can be delayed
leaving DOUT in a high-impedance condition. Pull CS
high after the 10th SCLK falling edge (see the Operating
Modes section).
The devices produce a digital output that corresponds to
the analog input voltage within the specified operating
range of 0 to V
V
Figure 6 shows an equivalent circuit for the analog input
AIN (for single-channel devices) and AIN1/AIN2 (for
dual-channel devices). Internal protection diodes D1/D2
confine the analog input voltage within the power rails
(V
GND - 0.3V to V
The electric load presented to the external stage driv-
ing the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
mode, the internal sampling capacitor C
be charged through the resistor R (R = 50I) to the input
voltage. For faithful sampling of the input, the capacitor
voltage on C
ing the track time.
Figure 7. Normal Mode
Figure 6. Analog Input Circuit
DOUT
SCLK
DD
DD
CS
for the single-channel devices.
, GND). The analog input voltage can swing from
IMPEDANCE
HIGH
AIN1/AIN2
AIN
S
1
has to settle to the required accuracy dur-
REF
DD
______________________________________________________________________________________
for the dual-channel devices and 0 to
+ 0.3V without damaging the device.
C
2
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
P
V
DD
D1
D2
3
SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
4
R
5
Analog Input
S
(16pF) has to
C
S
6
7
2Msps/3Msps, Low-Power,
VALID DATA
Serial 12-/10-/8-Bit ADCs
8
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows
THD sensitivity as a function of the signal source imped-
ance. Keep the source impedance at a minimum for
high-dynamic performance applications. Use a high-
performance op amp such as the MAX4430 to drive the
analog input, thereby decoupling the signal source and
the ADC.
While the ADC is in conversion mode, the sampling
switch is open presenting a pin capacitance, C
= 5pF), to the driving stage. See the Applications
Information section for information on choosing an
appropriate buffer for the ADC.
The output format is straight binary. The code transi-
tions midway between successive integer LSB values
such as 0.5 LSB, 1.5 LSB, etc. The LSB size for single-
channel devices is V
is V
characteristic is shown in Figure 10.
The ICs offer two modes of operation: normal mode and
power-down mode. The logic state of the CS signal
during a conversion activates these modes. The power-
down mode can be used to optimize power dissipation
with respect to sample rate.
In normal mode, the devices are powered up at all times,
thereby achieving their maximum throughput rates.
Figure 7 shows the timing diagram of these devices in
normal mode. The falling edge of CS samples the analog
input signal, starts a conversion, and frames the serial
data transfer.
REF
9
/2
n ,
10
where n is the resolution. The ideal transfer
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
11
DD
/2
12
n
ADC Transfer Function
and for dual-channel devices
13
Operating Modes
14
Normal Mode
15
IMPEDANCE
HIGH
16
P
(C
23
P