MRF89XAM9A-I/RM Microchip Technology, MRF89XAM9A-I/RM Datasheet - Page 75

• Manufacturer Part Number: MRF89XAM9A-I/RM
• Description: WiFi / 802.11 Modules & Development Tools 915MHz Sub-GHz Transceiver Mod
• Manufacturer: Microchip Technology

Specifications of MRF89XAM9A-I/RM

• Modulation Type: FSK, OOK
• Data Rate Max: 200Kbps
• Sensitivity: -113dBm
• Supply Voltage Range: 2.1V To 3.6V
• Module Interface: SPI, 4-Wire
• Supply Current: 25mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• Interrupt Requests (IRQ0 and IRQ1) during FIFO
FIGURE 3-14:
All the other interrupts through RSSI, SYNC, Payload,
WRITEBYTE, DCLK, PLL Lock are handled through
either of these interrupts discussed prior.
© 2010 Microchip Technology Inc.
operations include:
- FIFO Full: FIFOFULL interrupt source is high
- FIFO Overrun Clear: FOVRRUN flag is set
- FIFO Empty: FIFOEMPTY interrupt source is
Note:
- FIFO Threshold: FIFO_THRESHOLD interrupt
1
0
IRQ source
when the last FIFO byte (that is, the entire
FIFO) is full; otherwise it is low.
when a new byte is written by the user (in TX
or Stand-by modes) or the Shift register (in
RX mode) while the FIFO is full. Data is lost
and the flag should be cleared by writing a ‘1’
(note that the FIFO will be cleared).
low when byte 0 (that is, whole FIFO) is
empty; otherwise, it is high.
source’s behavior depends on the running
mode (TX, RX or Stand-by modes) and the
threshold itself can be programmed through
the FIFOCREG (B value). This behavior is
illustrated in Figure 3-14.
When retrieving data from the FIFO,
FIFOEMPTY is updated on CSDAT falling
edge (that is, when FIFOEMPTY is
updated to low state the currently started
read operation must be completed). In
other words, the FIFOEMPTY state must
be checked after each read operation for a
decision on the next one (FIFOEMPTY =
1: more byte(s) to read; FIFOEMPTY = 0:
no more bytes to read).
TX
RX and Stand-by
THRESHOLD IRQ
SOURCE BEHAVIOR
B
B+1 B+2
Number of
bytes in FIFO
Preliminary
3.6.3
Table 3-3 below summarizes the status of the FIFO
when switching between different modes.
TABLE 3-3:
3.6.4
The registers associated with FIFO and Interrupts are:
• GCONREG (Register 2-1)
• DMODREG (Register 2-2)
• FDEVREG (Register 2-3)
• BRSREG (Register 2-4)
• FLTHREG (Register 2-5)
• FIFOCREG (Register 2-6)
• FTXRXIREG (Register 2-14)
• FTPRIREG (Register 2-15)
• RSTHIREG (Register 2-16)
• FILCREG (Register 2-17)
• PFCREG (Register 2-18)
• SYNCREG (Register 2-19)
• RSTSREG (Register 2-21)
• OOKCREG (Register 2-22)
• FCRCREG (Register 2-32)
Stand-by TX
Stand-by RX
RX
RX
TX
TX
Any
From
TX
Stand-by Not cleared In Packet and
RX
Stand-by Not cleared
Sleep
FIFO CLEARING
FIFO AND INTERRUPT REGISTERS
To
STATUS OF FIFO WHEN
SWITCHING BETWEEN
DIFFERENT MODES OF THE
CHIP
Cleared
Not cleared In Packet mode,
Cleared
Cleared
Cleared
Cleared
Status
FIFO
MRF89XA
In Buffered mode,
FIFO cannot be
written in Stand-by
before TX
FIFO can be
written in Stand-by
before TX
Buffered modes,
FIFO can be read
in Stand-by after
RX
DS70622B-page 75
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