MRF89XAM9A-I/RM Microchip Technology, MRF89XAM9A-I/RM Datasheet - Page 81

• Manufacturer Part Number: MRF89XAM9A-I/RM
• Description: WiFi / 802.11 Modules & Development Tools 915MHz Sub-GHz Transceiver Mod
• Manufacturer: Microchip Technology

Specifications of MRF89XAM9A-I/RM

• Modulation Type: FSK, OOK
• Data Rate Max: 200Kbps
• Sensitivity: -113dBm
• Supply Voltage Range: 2.1V To 3.6V
• Module Interface: SPI, 4-Wire
• Supply Current: 25mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.10
In Buffered mode operation the NRZ data to/from the
(de)modulator is not directly accessed by the host
microcontroller but is stored in the FIFO and accessed
via the SPI data interface. This frees the host
microcontroller for other tasks between processing
data from the MRF89XA. Furthermore, it simplifies
software
microcontroller performance requirements (i.e., speed,
response). Note that in this mode the packet handler
stays inactive. The interface for Buffer mode is shown
in Figure 3-21.
An important feature is also the ability to empty the
FIFO in Stand-by mode, ensuring low power
consumption and adding greater software flexibility.
FIGURE 3-21:
© 2010 Microchip Technology Inc.
Note:
Data
Buffered Mode
Datapath
development
In this case Bit Synchronizer is automati-
cally enabled in Buffered mode. The Sync
word
(SYNCREN = 1) independently of the
FIFO filling method selected (FIFOFM).
TX
RX
Recognition
recognition
SYNC
BUFFERED MODE BLOCK DIAGRAM
overhead
must
and
be
MRF89XA
enabled
reduces
Preliminary
Control
(+SR)
FIFO
3.10.1
After entering TX in Buffered mode, the MRF89XA
expects the host microcontroller to write to the FIFO,
through the SPI data interface, all the data bytes to be
transmitted (preamble, Sync word, payload).
Actual transmission of the first byte will start either
when the FIFO is not empty (that is, first byte written by
the host microcontroller) or when the FIFO is full
depending on the IRQ0TXST bit (FTPRIREG<4>) set-
ting.
In Buffered mode the packet length is not limited, as
long as there are bytes inside the FIFO to be sent. When
the last byte is transferred to the SR, the FIFOEMPTY
IRQ
microcontroller, at that time the FIFO can still be filled
with additional bytes if required.
When the last bit of the last byte has left the Shift Reg-
ister (SR) (that is, eight bit periods later), the TXDONE
interrupt source is issued and the user can exit TX
mode after waiting at least one bit period from the last
bit processed by the modulator. If the transmitter is
switched OFF during transmission (for example, for
entering another chip mode), it will stop immediately,
even if there is still unsent data.
source
TX PROCESSING
is
CONFIG
DATA
issued
SPI
MRF89XA
to
interrupt
DS70622B-page 81
CSCON
SDO
SCK
SDI
IRQ1
CSDAT
IRQ0
the
host