AD5725BRSZ-500RL7 Analog Devices Inc, AD5725BRSZ-500RL7 Datasheet - Page 15

• Manufacturer Part Number: AD5725BRSZ-500RL7
• Description: IC,D/A CONVERTER,QUAD,12-BIT,CMOS,SSOP,28PIN
• Manufacturer: Analog Devices Inc

Specifications of AD5725BRSZ-500RL7

• Settling Time: 7µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 270mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Number Of Channels: 4
• Resolution: 12b
• Interface Type: Parallel
• Single Supply Voltage (typ): 9/12V
• Dual Supply Voltage (typ): ±9/±12V
• Architecture: R-2R
• Power Supply Requirement: Single/Dual
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 5V
• Single Supply Voltage (max): 15V
• Dual Supply Voltage (min): 0/5V
• Dual Supply Voltage (max): ±15V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5725BRSZ-500RL7; AD5725BRSZ-500RL7TR

THEORY OF OPERATION
The AD5725 is a quad voltage output, 12-bit parallel input DAC
featuring a 12-bit data bus with readback capability. The AD5725
operates from single or dual supplies ranging from +5 V up to
±15 V. The output voltage range is set by the reference voltages
applied at the V
DAC ARCHITECTURE
Each of the four DACs is a voltage switched, high impedance
(50 kΩ), R-2R ladder configuration. Each 2R resistor is driven
by a pair of switches that connect the resistor to either V
or V
OUTPUT AMPLIFIERS
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 500 pF to DGND. The source and sink
capabilities of the output amplifiers can be seen in Figure 23
and Figure 24. The slew rate is 2.2 V/μs with a full-scale settling
time of 10 μs. The amplifiers are short-circuit protected.
Careful attention to grounding is important for accurate
operation of the AD5725. With four outputs and two references
there is potential for ground loops. Since the AD5725 has no
analog ground, the ground must be specified with respect to the
reference.
REFERENCE INPUTS
All four DACs share common positive reference (V
negative reference (V
reference inputs set the output high and low voltage limits on all
four of the DACs. Each reference input has voltage restrictions
with respect to the other reference and to the power supplies.
V
V
V
AD5725 references cannot be inverted (V
greater than V
It is important to note that the AD5725 V
and sources current. Also, the input current of both V
V
sinking capability and must be buffered with an amplifier to
drive V
requirements.
It is recommended that the reference inputs be bypassed with
0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.
REFN
REFP
REFN
REFN
REFL
can be any value between AV
can be any voltage between AV
+ 2.5 V. Note that because of these restrictions, the
are code dependent. Many references have limited current
REFP
.
. The V
REFP
REFP
).
REFN
and V
REFN
reference input has no such special
) inputs. The voltages applied to these
REFN
pins.
DD
SS
– 2.5 V and
and V
REFN
REFP
REFP
input both sinks
cannot be
− 2.5 V and
REFP
REFP
) and
REFH
and
Rev. A | Page 15 of 20
PARALLEL INTERFACE
See Table 7 for the digital control logic truth table. The parallel
interface consists of a 12-bit bidirectional data bus, two register
select inputs, A0 and A1, a R/ W input, a chip select ( CS ), and a
load DAC ( LDAC ) input. Control of the DACs and bus
direction is determined by these inputs as shown in
Digital data bits are labeled with the MSB defined as Data Bit 11
and the LSB as Data Bit 0. All digital pins are TTL/CMOS
compatible.
The register select inputs A0 and A1 select individual DAC
Register A (Binary Code 00) through Register D (Binary Code 11).
Decoding of the registers is enabled by the CS input. When CS
is high, no decoding takes place, and neither the writing nor the
reading of the input registers is enabled. The loading of the
second bank of registers is controlled by the asynchronous
LDAC input. By taking LDAC low while CS is high, all output
registers can be updated simultaneously. Note that the t
required pulse width for updating all DACs is a minimum of
10 ns. The R/ W input, when enabled by CS , controls the writing
to and reading from the input register.
DATA CODING
The AD5725 uses binary coding. The output voltage can be
calculated as follows:
where D is the digital code in decimal.
CLR
The CLR function can be used either at power-up or at any time
during the DACs operation. The CLR function is independent
of CS . This pin is active low and sets the DAC registers to either
midscale code (0x800) for the AD5725 or zero code (0x000) for
the AD5725-1. The CLR to midscale code is most useful when
the DAC is configured for bipolar references and an output of
0 V is desired.
V
OUT
=
V
REFN
+
(
V
REFP
−
4096
V
REFN
)
×
D
AD5725
Table 7
LDW
.