AD606JN Analog Devices Inc, AD606JN Datasheet - Page 5

• Manufacturer Part Number: AD606JN
• Description: Amplifier IC
• Manufacturer: Analog Devices Inc

Specifications of AD606JN

• No. Of Amplifiers: 1
• Bandwidth: 50MHz
• No. Of Pins: 16
• Mounting Type: Through Hole
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package / Case: 16-DIP
• Rohs Status: RoHS non-compliant
• Amplifier Type: Logarithmic
• Number Of Circuits: 1
• Output Type: Differential
• Current - Input Bias: 4µA
• Current - Supply: 13mA
• Current - Output / Channel: 1.2mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• -3db Bandwidth: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

for that converter should be a fractional part of V
The slope is essentially independent of temperature.
The intercept P
voltage or temperature. However, the AD606 is not factory
calibrated, and both the slope and intercept may need to be
externally adjusted. Following calibration, the conformance to
an ideal logarithmic law will be found to be very close, particu-
larly at moderate frequencies (see Figure 14), and still accept-
able at the upper end of the frequency range (Figure 15).
CIRCUIT DESCRIPTION
Figure 2 is a block diagram of the AD606, which is a complete
logarithmic amplifier system in monolithic form. It uses a total
of nine limiting amplifiers in a “successive detection” scheme to
closely approximate a logarithmic response over a total dynamic
range of 90 dB (Figure 2). The signal input is differential, at
nodes INHI and INLO, and will usually be sinusoidal and ac
coupled. The source may be either differential or single-sided;
the input impedance is about 2.5 k in parallel with 2 pF. Seven
of the amplifier/detector stages handle inputs from –80 dBm
(32 V rms) up to about –14 dBm (45 mV rms). The noise floor
is about –83 dBm (18 V rms). Another two stages receive the
input attenuated by 22.3 dB, and respond to inputs up to
+10 dBm (707 mV rms). The gain of each of these stages is
11.15 dB and is accurately stabilized over temperature by a
precise biasing system.
The detectors provide full-wave rectification of the alternating
signal present at each limiter output. Their outputs are in the
form of currents, proportional to the supply voltage. Each cell
incorporates a low-pass filter pole, as the first step in recovering
the average value of the demodulated signal, which contains
appreciable energy at even harmonics of the input frequency. A
further real pole can be introduced by adding a capacitor be-
tween the summing node ISUM and VPOS. The summed de-
tector output currents are applied to a 6:1 reduction current
mirror. Its output at ILOG is scaled 2 A/dB, and is converted
to voltage by an internal load resistor of 9.375 k between
REV. B
X
is essentially independent of either the supply
INLO
INHI
16
1
30k
1.5k
1.5k
AD606
250
COMM
COMM
15
2
30k
DETECTORS
HIGH-END
AND POWER-UP
REFERENCE
Figure 2. Simplified Block Diagram
PRUP
ISUM
POS
14
3
, if possible.
12 A/dB
2 A/dB
ONE-POLE
FILTER
VPOS
ILOG
13
4
–5–
X1
9.375k
9.375k
ILOG and OPCM (output common, which is usually grounded).
The nominal slope at this point is 18.75 mV/dB (375 mV/
decade).
In applications where V
allows the use of an external reference, this reference input
should also be connected to the same +5 V supply. The power
supply voltage may be in the range +4.5 V to +5.5 V, providing
a range of slopes from nominally 33.75 mV/dB (675 mV/ de-
cade) to 41.25 mV/dB (825 mV/decade).
A buffer amplifier, having a gain of two, provides a final output
scaling at V
impedance output can run from close to ground to over +4 V
(using the recommended +5 V supply) and is tolerant of resis-
tive and capacitive loads. Further filtering is provided by a con-
jugate pole pair, formed by internal capacitors which are an
integral part of the output buffer. The corner frequency of the
overall filter is 2 MHz, and the 10%–90% rise time is 150 ns.
Later, we will show how the slope and intercept can be altered
using simple external adjustments. The direct buffer input
BFIN is used in these cases.
The last limiter output is available as complementary currents
from open collectors at pins LMHI and LMLO. These currents
are each 1.2 mA typical with LADJ grounded and may be con-
verted to voltages using external load resistors connected to
VPOS; typically, a 200
The voltage gain is then over 90 dB, resulting in a hard-limited
output for all input levels down to the noise floor. The phasing
is such that the voltage at LMHI goes high when the input
(INHI to INLO) is positive. The overall delay time from the
signal inputs to the limiter outputs is 8 ns. Of particular impor-
tance is the phase stability of these outputs versus input level. At
50 MHz, the phase typically remains within 4 from –70 dBm
to +5 dBm. The rise time of this output (essentially a square
wave) is about 1.2 ns, resulting in clean operation to more than
70 MHz.
BFIN
FIL1
30pF
MAIN SIGNAL PATH
12
5
11.15dB/STAGE
2pF
LOW-PASS FILTER
30pF
2pF
OFFSET-NULL
LOG
X2
VLOG
SALLEN-KEY
FIL2
TWO-POLE
11
6
FILTER
of 37.5 mV/dB (750 mV/decade). This low-
360k
360k
LOG
OPCM
LADJ
10
7
resistor is used on just one output.
is taken to an A/D converter which
LIMITER
FINAL
LMLO
LMHI
9
8
AD606