AD606JN Analog Devices Inc, AD606JN Datasheet - Page 6

• Manufacturer Part Number: AD606JN
• Description: Amplifier IC
• Manufacturer: Analog Devices Inc

Specifications of AD606JN

• No. Of Amplifiers: 1
• Bandwidth: 50MHz
• No. Of Pins: 16
• Mounting Type: Through Hole
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package / Case: 16-DIP
• Rohs Status: RoHS non-compliant
• Amplifier Type: Logarithmic
• Number Of Circuits: 1
• Output Type: Differential
• Current - Input Bias: 4µA
• Current - Supply: 13mA
• Current - Output / Channel: 1.2mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• -3db Bandwidth: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD606
Offset-Control Loop
The offset-control loop nulls the input offset voltage, and sets
up the bias voltages at the input pins INHI and INLO. A full
understanding of this offset-control loop is useful, particularly
when using larger input coupling capacitors and an external
filter capacitor to lower the minimum acceptable operating
frequency. The loop’s primary purpose is to extend the lower
end of the dynamic range in the case where the offset voltage of
the first stage should be high enough to cause later stages to
prematurely enter limiting, because of the high dc gain (about
8000) of the main amplifier system. For example, an offset
voltage of only 20 V would become 160 mV at the output of
the last stage in the main amplifier (before the final limiter sec-
tion), driving the last stage well into limiting. In the absence of
noise, this limiting would simply result in the logarithmic output
ceasing to become any lower below a certain signal level at the
input. The offset would also degrade the logarithmic conform-
ance in this region. In practice, the finite noise of the first stage
also plays a role in this regard, even if the dc offset were zero.
Figure 3 shows a representation of this loop, reduced to essen-
tials. The figure closely corresponds to the internal circuitry,
and correctly shows the input resistance. Thus, the forward gain
of the main amplifier section is 7 11.15 dB, but the loop gain
is lowered because of the attenuation in the network formed by
RB1 and RB2 and the input resistance RA. The connection
polarity is such as to result in negative feedback, which reduces
the input offset voltage by the dc loop gain, here about 50 dB,
that is, by a factor of about 316. We use a differential representa-
tion, because later we will examine the consequences to the
power-up response time in the event that the ac coupling capaci-
tors C
tors, as well as forming a high-pass filter to the signal in the
forward path, also introduce a pole in the feedback path.
Internal resistors RF1 and RF2 in conjunction with grounded
capacitors CF1 and CF2 form a low-pass filter at 15 kHz. This
frequency can optionally be lowered by the addition of an exter-
nal capacitor C
conjunction with the low-pass section formed at the input cou-
pling, results in a two-pole high-pass response, falling of at
40 dB/decade below the corner frequency. The damping factor
of this filter depends on the ratio C
also on the value of R
The inclusion of this control loop has no effect on the high frequency
response of the AD606. Nor does it have any effect on the low fre-
quency response when the input amplitude is substantially above the
input offset voltage.
C1
C
C
and C
C1
C2
RB1
30k
RA
2.5k
RB2
30k
C2
Z
Figure 3. Offset Control Loop
, and in some cases a series resistor R
do not exactly match. Note that these capaci-
78dB
Z
.
+1
+1
CF2
30pF
CF1
30pF
Z
/C
0V
C
(when C
RF2
360k
RF1
360k
TO FINAL
LIMITER
STAGE
Z
FIL2
FIL1
>>C
Z
C
R
. This, in
F
Z
Z
) and
–6–
The loop’s effect is felt only at the lower end of the dynamic
range, that is, from about 80 dBm to –70 dBm, and when the
signal frequency is near the lower edge of the passband. Thus,
the small signal results which are obtained using the suggested
model are not indicative of the ac response at moderate to high
signal levels. Figure 4 shows the response of this model for the
default case (using C
150 pF. In general, a maximally flat ac response occurs when C
is roughly twice C
30 pF capacitors). Thus, for audio applications, one can use
C
(–3 dB) at 25 Hz.
Figure 4. Frequency Response of Offset Control Loop for
C
However, the maximally flat ac response is not optimal in two
special cases. First, where the RF input level is rapidly pulsed,
the fast edges will cause the loop filter to ring. Second, ringing
can also occur when using the power-up feature, and the ac
coupling capacitors do not exactly match in value. We will ex-
amine the latter case in a moment. Ringing in a linear amplifier
is annoying, but in a log amp, with its much enhanced sensitiv-
ity to near zero signals, it can be very disruptive.
To optimize the low level accuracy, that is, achieve a highly
damped pulse response in this filter, it is recommended to in-
clude a resistor R
experimentation may be necessary, but for operation in the
range 3 MHz to 70 MHz, values of C
and R
use C
typical connections for the AD606 with these filter components
added.
Z
C
= 0 pF and C
= 2.7 F and C
Figure 5. Use of C
Compensation
C
Z
–10
–20
= 2 k are near optimal. For operation down to 100 kHz
= 10 nF, C
90
80
70
60
50
40
30
20
10
0
10k
Z
Z
C
C
= 150 pF (C
Z
Z
Z
in series with an increased value of C
= 150pF
100k
(making due allowance for the internal
= 0.1 F and R
= 4.7 F to achieve a high-pass corner
C
= 100 pF and C
INPUT FREQUENCY – Hz
Z
and R
AD606JN
C
C
C
Z
1M
Z
Z
= 0pF
= 100 pF)
for Offset Control Loop
Z
C
= 13 k . Figure 5 shows
Z
= 100 pF, C
R
Z
= 0) and with C
10M
Z
= 1 nF
100M
Z
REV. B
Z
. Some
=
Z