AD6642BBCZ Analog Devices Inc, AD6642BBCZ Datasheet - Page 20

• Manufacturer Part Number: AD6642BBCZ
• Description: 11Bit 200Msps Dual IF Diversity Receiver
• Manufacturer: Analog Devices Inc

Specifications of AD6642BBCZ

• Function: IF Receiver
• Frequency: 0Hz ~ 800MHz
• Rf Type: CDMA, LTE, W-CDMA, WiMAX
• Package / Case: 144-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD6642
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNR
can be calculated by
In the equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as illustrated in Figure 43.
The clock input should be treated as an analog signal in cases
in which aperture jitter may affect the dynamic range of the
AD6642. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or another
method), it should be retimed by the original clock at the last
step. Refer to Application Note AN-501 and Application Note
AN-756 for more information about jitter performance as it
relates to ADCs (see www.analog.com).
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD6642 is proportional to its clock
rate (see Figure 44). The digital power dissipation does not vary
significantly because it is determined primarily by the DRVDD
supply and the bias current of the LVDS drivers.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 44 was
taken using the same operating conditions as those used in the
Typical Performance Characteristics section, with a 5 pF load
on each output driver.
SNR
80
75
70
65
60
55
50
1
HF
LF
= −10log[(2π × f
) at a given input frequency (f
Figure 43. SNR vs. Input Frequency and Jitter
INPUT FREQUENCY (MHz)
10
IN
× t
JRMS
)
2
+ 10
100
IN
(−SNR LF /10)
) due to jitter (t
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
]
1k
JRMS
Rev. A | Page 20 of 32
)
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6642 is placed in power-down
mode. In this state, the ADC typically dissipates 4.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD6642 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode; shorter power-down cycles
result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map
Register Descriptions section for more details.
CHANNEL/CHIP SYNCHRONIZATION
The AD6642 has a SYNC input that offers the user flexible syn-
chronization options for synchronizing the clock divider. The
clock divider sync feature is useful for guaranteeing synchronized
sample clocks across multiple ADCs.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Figure 44. Power and Current vs. Sampling Frequency
SAMPLING FREQUENCY (MSPS)
TOTAL POWER
I
AVDD
I
DRVDD
0.30
0.25
0.20
0.15
0.10
0.05
0