AD6657BBCZ Analog Devices Inc, AD6657BBCZ Datasheet - Page 11

• Manufacturer Part Number: AD6657BBCZ
• Description: 11 Bit 185 Msps Quad IF Receiver
• Manufacturer: Analog Devices Inc

Specifications of AD6657BBCZ

• Function: IF Receiver
• Frequency: 0Hz ~ 800MHz
• Rf Type: CDMA, LTE, W-CDMA, WiMAX
• Package / Case: 144-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No.
M7
L7
K8
J8
M8
L8
K9
J9
M9
L9
K10
J10
M10
L10
K11
J11
M11
L11
K12
J12
M12
L12
K1
J1
M1
L1
K2
J2
M2
L2
K3
J3
M3
L3
K4
J4
M4
L4
K5
J5
M5
L5
K6
J6
M6
L6
C9
C8
C7
C6
C5
C4
Mnemonic
D1+AB
D1−AB
D2+AB
D2−AB
D3+AB
D3−AB
D4+AB
D4−AB
D5+AB
D5−AB
D6+AB
D6−AB
D7+AB
D7−AB
D8+AB
D8−AB
D9+AB
D9−AB
D10+AB
D10−AB
DCO+AB
DCO−AB
D0+CD
D0−CD
D1+CD
D1−CD
D2+CD
D2−CD
D3+CD
D3−CD
D4+CD
D4−CD
D5+CD
D5−CD
D6+CD
D6−CD
D7+CD
D7−CD
D8+CD
D8−CD
D9+CD
D9−CD
D10+CD
D10−CD
DCO+CD
DCO−CD
MODE
SYNC
PDWN
SCLK
SDIO
CSB
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/output
Input
Rev. A | Page 11 of 32
Channel A and Channel B LVDS Output Data 1—True
Channel A and Channel B LVDS Output Data 1—Complement
Channel A and Channel B LVDS Output Data 2—Complement
Channel A and Channel B LVDS Output Data 3—True
Channel A and Channel B LVDS Output Data 3—Complement
Channel A and Channel B LVDS Output Data 4—Complement
Channel A and Channel B LVDS Output Data 5—True
Channel A and Channel B LVDS Output Data 5—Complement
Channel A and Channel B LVDS Output Data 6—True
Channel A and Channel B LVDS Output Data 6—Complement
Channel A and Channel B LVDS Output Data 7—True
Channel A and Channel B LVDS Output Data 7—Complement
Channel A and Channel B LVDS Output Data 8—True
Channel A and Channel B LVDS Output Data 8—Complement
Channel A and Channel B LVDS Output Data 9—True
Channel A and Channel B LVDS Output Data 9—Complement
Channel A and Channel B LVDS Output Data 10—True
Channel A and Channel B LVDS Output Data 10—Complement
Channel C and Channel D LVDS Output Data 0—True
Channel C and Channel D LVDS Output Data 0—Complement
Channel C and Channel D LVDS Output Data 1—True
Channel C and Channel D LVDS Output Data 1—Complement
Channel C and Channel D LVDS Output Data 2—True
Channel C and Channel D LVDS Output Data 2—Complement
Channel C and Channel D LVDS Output Data 3—True
Channel C and Channel D LVDS Output Data 3—Complement
Channel C and Channel D LVDS Output Data 4—True
Channel C and Channel D LVDS Output Data 4—Complement
Channel C and Channel D LVDS Output Data 5—True
Channel C and Channel D LVDS Output Data 5—Complement
Channel C and Channel D LVDS Output Data 6—True
Channel C and Channel D LVDS Output Data 6—Complement
Channel C and Channel D LVDS Output Data 7—True
Channel C and Channel D LVDS Output Data 7—Complement
Channel C and Channel D LVDS Output Data 8—True
Channel C and Channel D LVDS Output Data 8—Complement
Channel C and Channel D LVDS Output Data 9—True
Channel C and Channel D LVDS Output Data 9—Complement
Channel C and Channel D LVDS Output Data 10—True
Channel C and Channel D LVDS Output Data 10—Complement
Data Clock LVDS Output for Channel C and Channel D—True
Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR)
Digital Synchronization Pin
SPI Clock
SPI Chip Select (Active Low)
Description
Channel A and Channel B LVDS Output Data 2—True
Channel A and Channel B LVDS Output Data 4—True
Data Clock LVDS Output for Channel A and Channel B—True
Data Clock LVDS Output for Channel A and Channel B—Complement
Data Clock LVDS Output for Channel C and Channel D—Complement
Power-Down Input (Active High)
SPI Data
AD6657