AD7712ARZ-REEL Analog Devices Inc, AD7712ARZ-REEL Datasheet - Page 7

• Manufacturer Part Number: AD7712ARZ-REEL
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7712ARZ-REEL

• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. F
Pin Mnemonic
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
SCLK
MCLK IN
MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
A0
SYNC
MODE
AIN1(+)
AIN1(–)
STANDBY
TP
V
AV
V
REF IN(–)
REF IN(+)
REF OUT
AIN2
AGND
TFS
RFS
SS
BIAS
DD
Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can
Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
Analog Input Channel 2. High level analog input that accepts an analog input voltage range of ± 4
Ground Reference Point for Analog Circuitry.
Function
Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes
active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7712 in smaller batches of data.
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.
Address Input. With this input low, reading and writing to the device is to the control register. With this input
high, access is to either the data register or the calibration registers.
Logic Input. Allows for synchronization of the digital filters when using a number of AD7712s. It resets
the nodes of the digital filter.
external clocking mode.
is connected to an output current source that can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.
Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 50 µW.
Test Pin. Used when testing the device. Do not connect anything to this pin.
Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1
should not go > 30 mV negative w.r.t. V
Analog Positive Supply Voltage, 5 V to 10 V.
Input Bias Voltage. This input voltage should be set such that V
and V
–5 V, it can be tied to AGND, while with AV
Reference Input. The REF IN(–) can lie anywhere between AV
than REF IN(–).
Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).
REF IN(+) can lie anywhere between AV
Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output
that is referred to AGND.
V
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word
is written to the part.
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external
clocking mode, the SDATA line becomes active after RFS goes low.
REF
V
REF
/GAIN. At the nominal V
SS
> V
. Thus, with AV
SS
where V
REF
DD
is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV
= +5 V and V
PIN FUNCTION DESCRIPTION
REF
of +2.5 V and a gain of 1, the AIN2 input voltage range is ± 10 V.
SS
SS
DD
for correct operation of the device.
–7–
= 0 V, it can be tied to REF OUT; with AV
and V
DD
= +10 V, it can be tied to +5 V.
SS
.
DD
BIAS
and V
+ 0.85
SS
provided REF IN(+) is greater
V
REF
< AV
DD
DD
= +5 V and V
and V
AD7712
BIAS
DD
– 0.85
SS
=