AD7713ARZ-REEL Analog Devices Inc, AD7713ARZ-REEL Datasheet - Page 4

• Manufacturer Part Number: AD7713ARZ-REEL
• Description: 24 BIT SIGMA DELTA ADC IC
• Manufacturer: Analog Devices Inc

Specifications of AD7713ARZ-REEL

• Number Of Bits: 24
• Sampling Rate (per Second): 205
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 5.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7713
Parameter
POWER REQUIREMENTS
NOTES
10
11
12
13
14
15
16
17
18
19
Specifications subject to change without notice.
1
2
3
4
5
6
7
8
9
These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV
Temperature range is: A Version, –40°C to +85°C; S Version, –55°C to +125°C.
Applies after calibration at the temperature of interest.
Positive full-scale error applies to both unipolar and bipolar input ranges.
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
These numbers are guaranteed by design and/or characterization.
The AIN1 and AIN2 analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recom-
mended source resistance depends on the selected gain.
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The input voltage
range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AV
negative than AGND – 30 mV.
V
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section of the specifications.
Guaranteed by design, not production tested.
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.
AGND – 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
Operating with AV
The ± 5% tolerance on the DV
Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, or 60 Hz.
PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
AIN3
Power Supply Voltages
Power Supply Currents
Power Supply Rejection
Power Dissipation
REF
Positive Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
AV
DV
AV
DV
(AV
Normal Mode
Standby (Power-Down) Mode
= REF IN(+) – REF IN(–).
DD
DD
DD
DD
DD
Voltage
Current
Voltage
Current
and DV
DD
16
17
voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0°C to 70°C temperature range.
DD
)
19
DD
18
input is allowed provided that DV
15
13
A, S Versions
+(4.2
0 to V
+(3.2
+(4.2
5 to 10
5
0.6
0.7
0.5
1
5.5
300
REF
V
V
V
/GAIN
DD
REF
REF
REF
does not exceed AV
)/GAIN V max
)/GAIN V min
)/GAIN V max
1
–4–
Unit
V max
V nom
V nom
mA max
mA max
mA max
mA max
dB typ
mW max
µW max
DD
by more than 0.3 V.
Conditions/Comments
GAIN Is the Selected PGA Gain
(Between 1 and 128).
GAIN Is the Selected PGA Gain
(Between 1 and 128).
GAIN Is the Selected PGA Gain
(Between 1 and 128).
GAIN Is the Selected PGA Gain
(Between 1 and 128).
± 5% for Specified Performance.
± 5% for Specified Performance.
AV
AV
f
Digital Inputs 0 V to DV
f
Digital Inputs 0 V to DV
Rejection w.r.t. AGND.
AV
Typically 3.5 mW.
AV
CLK IN
CLK IN
DD
DD
DD
DD
= 5 V.
= 10 V.
= DV
= DV
= 1 MHz.
= 2 MHz.
DD
DD
DD
+ 30 mV and AGND – 30 mV.
= 5 V, f
= 5 V, Typically 150 µW.
DD
+ 30 mV or go more negative than
CLK IN
DD
DD
DD
.
.
= 1 MHz;
+ 30 mV or more
REV. D