AD7713 Analog Devices, AD7713 Datasheet
AD7713
Specifications of AD7713
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AD7713 Summary of contents
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... PDIP and CERDIP as well as a 24- REF lead SOIC package. PRODUCT HIGHLIGHTS 1. The AD7713 consumes less than total supply current, making it ideal for use in loop-powered systems. 2. The two programmable gain channels allow the AD7713 to accept input signals directly from a transducer removing a considerable amount of signal conditioning ...
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... AD7713–SPECIFICATIONS MCLK MHz, unless otherwise noted. All specifications T Parameter STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity Positive Full-Scale Error 5 Full-Scale Drift 2, 4 Unipolar Offset Error 5 Unipolar Offset Drift 2, 4 Bipolar Zero Error 5 Bipolar Zero Drift Gain Drift ...
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... V max REF –(1.05 V )/GAIN V max REF +(0.8 V )/GAIN V min REF +(2.1 V )/GAIN V max REF –3– AD7713 Conditions/Comments Functional with Lower V Voltages. REF For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0. NOTCH For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0. NOTCH At DC ...
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... This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV 11 This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset drift on the AIN3 input is four times the value given in the Static Performance section of the specifications. ...
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... See Figures 10 to 13. 3 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7713 is production tested with MHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7713 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. SYNC 5 Logic Input. Allows for synchronization of the digital filters when using a number of AD7713s. It resets the nodes of the digital filter. 6 MODE Logic Input ...
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... AD7713 can accept and still calibrate offset accurately. Full-Scale Calibration Range This is the range of voltages that the AD7713 can accept in the system calibration mode and still calibrate full scale correctly. Input Span In system calibration schemes, two voltages applied in sequence to the AD7713’ ...
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... Activate Background Calibration. This activates background calibration on the channel selected by CH0 and CH1. If the background calibration mode is on, the AD7713 provides continuous self-calibration of the refer- ence and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. Its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature ...
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... FS11 and is in the range 19 to 2,000. With the nominal MHz, this results in a first notch frequency range from 1.952 Hz to 205.59 kHz. To ensure correct operation of the AD7713, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. ...
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... V /GAIN, i.e., the input full scale REF Gain of 32 Gain of 64 Gain of 128 0.25 0.25 0.25 0.44 0.41 0.38 0.46 0.43 0.4 0.54 0.46 0.46 0.63 0.62 0.6 1.1 0.9 0.65 7 180 120 70 Gain of 32 Gain of 64 Gain of 128 20.5 19.5 18.5 19.5 18.5 17.5 19.5 18.5 17.5 19 18.5 17 17.5 17 15.5 15 12.5 12 /GAIN). Table II applies for a V REF AD7713 0.25 0.38 0.4 0.46 0.56 0.65 1 17.5 16.5 16.5 16 14.5 12 2.5 V REF ...
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... Figure 2b. Plot of Output Noise vs. Gain and Notch Frequency (Gains 128) CIRCUIT DESCRIPTION The AD7713 ADC with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals, such as those in industrial control or process control applications. It contains a - (or charge balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter, and a bidirectional serial communications port ...
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... Number of Bits a 1-bit ADC or comparator yields an SNR of 7.78 dB. The AD7713 samples the input signal at a frequency of 7.8 kHz or greater (see Table III result, the quantization noise is spread over a much wider frequency than that of the band of interest. The noise in the band of interest is reduced still fur- ...
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... AD7713. For example, if the required bandwidth is 1.57 Hz but the required update rate is 20 Hz, the data can be taken from the AD7713 at the 20 Hz rate giving a –3 dB bandwidth of 5.24 Hz. Post filtering can be applied to this to reduce the bandwidth and output noise, to the 1 ...
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... TC resistor to generate the reference voltage for the part. In this case 12.5 kΩ resistor is used, the 200 µA current source generates 2.5 V across the resistor. This 2.5 V can be applied to the REF IN(+) input of the AD7713 V BIAS and the REF IN(–) input at ground will supply a V the part. For 3-wire RTD configurations, the reference voltage for the part is generated by placing a low TC resistor (12.5 kΩ ...
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... AD7713 are acceptable, and no calibration is performed after power-on, issuing a SYNC pulse to the AD7713 will reset the AD7713’s digital filter logic the SYNC line, with R, C time constant longer than the DV time, will perform the SYNC function. ...
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... MD2, MD1, and MD0 of the control register. When invoked, the background calibration mode reduces the output data rate of the AD7713 by a factor of 6 while the –3 dB bandwidth remains unchanged. Its advantage is that the part is continually per- forming calibration and automatically updating its calibration coefficients ...
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... The AD7713’s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers, and digital signal processors. A serial read to the AD7713 can access data from the output register, the control register, or from the calibration registers. A serial write to the AD7713 can write data to the control register or the calibration registers ...
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... SCLK output. With DRDY low, the RFS input is brought low. RFS going low enables the serial clock of the AD7713 and also places the MSB of the word on the serial data line. All subsequent data bits are clocked out on a high-to-low transition of the serial clock and are valid prior to the following rising edge of this clock ...
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... Figures 12a and 12b show timing diagrams for reading from the AD7713 in the external clocking mode. Figure 12a shows a situation where all the data is read from the AD7713 in one read operation. Figure 12b shows a situation where the data is read from the AD7713 over a number of read operations. Both read operations show a read from the AD7713’ ...
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... Data to be loaded to the AD7713 must be valid prior to the rising edge of the SCLK signal. TFS should return high during the low time of SCLK. After TFS returns low again, the next bit of the data-word to be loaded to the AD7713 is clocked in on REV ...
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... This depends on whether the first bit transmitted by the microprocessor is the MSB or the LSB. The AD7713 expects the MSB as the first bit in the data stream. In cases where the data is being read or being written in bytes and the data has to be reversed, the bits will have to be reversed for every byte ...
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... The AD7713 is configured for its exter- nal clocking mode, while the SPI port is used on the 68HC11, which is in its single chip mode. The DRDY line from the AD7713 is connected to the Port PC2 input of the 68HC11, so the DRDY line is polled by the 68HC11. The DRDY line can be connected to the IRQ input of the 68HC11 if an interrupt driven system is preferred ...
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... RTD is 100 Ω and, therefore, the RTD will generate signal, which can be handled directly by the analog input of the AD7713. In the circuit shown, the second RTD excitation current is used to generate the reference voltage for the AD7713. This reference voltage is developed across R and applied to the differential reference inputs ...
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... IN(– 4.5 A AIN1(+) AIN1(–) AIN2 – 128 200 A RTD1 200 A RTD2 AD7711 AGND DGND V SS –25– AD7713 REF REF V REF OUT IN(+) BIAS 2.5V REFERENCE CHARGING BALANCING A/D CONVERTER AUTO-ZEROED DIGITAL SYNC – FILTER MODULATOR PGA MCLK – 128 ...
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... AD7713 AD7712 FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity High Level and Low Level Analog Input Channels Programmable Gain for Both Inputs Gains from 1 to 128 Differential Input for Low Level Channel Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients ...
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... CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –27– 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45 0.25 (0.0098 1.27 (0.0500) 0.40 (0.0157) AD7713 ...
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... Sheet changed from REV REV. D. Updated layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to Self-Calibration section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Changes to AD7713 to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Deleted AD7713 to ADSP-2105 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Deleted Figure 19 and renumbered succeeding figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 –28– Page REV. D ...