AD7713 Analog Devices, AD7713 Datasheet - Page 13

• Manufacturer Part Number: AD7713
• Description: CMOS, Low Power 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Current Sources
• Manufacturer: Analog Devices

Specifications of AD7713

• Resolution (bits): 24bit
• # Chan: 3
• Sample Rate: 3.9kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p,Uni (Vref) x 4,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

The AD7713 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the device’s calibra-
tion coefficients and also to write its own calibration coefficients
to the part from prestored values in E
microprocessor much greater control over the AD7713’s calibra-
tion procedure. It also means that the user can verify that the
device has performed its calibration correctly by comparing the
coefficients after calibration with prestored values in E
For battery-operated or low power systems, the AD7713 offers
a standby mode (controlled by the STANDBY pin) that reduces
idle power consumption to typically 150 µW.
THEORY OF OPERATION
The general block diagram of a - ADC is shown in Figure 4.
It contains the following elements:
• A sample-hold amplifier
• A differential amplifier or subtracter
• An analog low-pass filter
• A 1-bit ADC (comparator)
• A 1-bit DAC
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
Oversampling is fundamental to the operation of - ADCs.
Using the quantization noise formula for an ADC
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7713 samples the input signal at a frequency of 7.8 kHz
or greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still fur-
ther by analog filtering in the modulator loop, which shapes
the quantization noise spectrum to move most of the noise
energy to frequencies outside the bandwidth of interest. The
noise performance is thus improved from this 1-bit level to the
performance outlined in Tables I and II and in Figures 2a and 2b.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data-word using a
digital filter.
REV. D
S/H AMP
SNR
=
Figure 4. General - ADC
(
6 02
.
×
Number of Bits
LOW-PASS
ANALOG
FILTER
DAC
2
COMPARATOR
PROM. This gives the
+
1 76
.
DIGITAL DATA
)
dB
DIGITAL
FILTER
2
PROM.
–13–
low-pass filter. A simple example of a first-order - ADC is
shown in Figure 5. This contains only a first-order low-pass
filter or integrator. It also illustrates the derivation of the alter-
native name for these devices: charge balancing ADCs.
It consists of a differential amplifier (whose output is the differ-
ence between the analog input and the output of a 1-bit DAC),
an integrator, and a comparator. The term charge balancing comes
from the fact that this system is a negative feedback loop that tries
to keep the net charge on the integrator capacitor at 0 by balanc-
ing charge injected by the input voltage with charge injected by
the 1-bit DAC. When the analog input is 0, the only contribu-
tion to the integrator output comes from the 1-bit DAC. For the
net charge on the integrator capacitor to be 0, the DAC output
must spend half its time at +FS and half its time at –FS. Assum-
ing ideal components, the duty cycle of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7713 uses a second-order - modulator and a digital
filter that provides a rolling average of the sampled output.
After power-up or if there is a step change in the input voltage,
there is a settling time that must elapse before valid data is
obtained.
Input Sample Rate
The modulator sample frequency for the device remains at
f
selected gain. However, gains greater than 1 are achieved by a
combination of multiple input samples per modulator cycle and
a scaling of the ratio of the reference capacitor to input capaci-
tor. As a result of the multiple sampling, the input the sample
rate of the device varies with the selected gain (see Table III).
The effective input impedance is 1/C
sampling capacitance and f
Gain
1
2
4
8
16
32
64
128
CLK IN
- ADCs are generally described by the order of the analog
/512 (3.9 kHz @ f
Table III. Input Sampling Frequency vs. Gain
Input Sampling Frequency (f
f
2
4
8
8
8
8
8
V
CLK IN
IN
Figure 5. Basic Charge-Balancing ADC
DIFFERENTIAL
f
f
f
f
f
f
f
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
AMPLIFIER
/256 (7.8 kHz @ f
/256 (15.6 kHz @ f
/256 (31.2 kHz @ f
/256 (62.4 kHz @ f
/256 (62.4 kHz @ f
/256 (62.4 kHz @ f
/256 (62.4 kHz @ f
/256 (62.4 kHz @ f
CLK IN
INTEGRATOR
S
is the input sample rate.
+FS
–FS
= 2 MHz) regardless of the
DAC
CLK IN
COMPARATOR
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
f
= 2 MHz)
S
S
, where C is the input
)
= 2 MHz)
= 2 MHz)
= 2 MHz)
= 2 MHz)
= 2 MHz)
= 2 MHz)
= 2 MHz)
AD7713