AD7713 Analog Devices, AD7713 Datasheet - Page 21

• Manufacturer Part Number: AD7713
• Description: CMOS, Low Power 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Current Sources
• Manufacturer: Analog Devices

Specifications of AD7713

• Resolution (bits): 24bit
• # Chan: 3
• Sample Rate: 3.9kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p,Uni (Vref) x 4,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

DRDY line will go high, turning off the SDATA output as per
Figure 12a.
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line, and the write operation does not have any
effect on the status of DRDY. A write operation to the control
register or the calibration register must always write 24 bits to
the respective register.
Figure 13a shows a write operation to the AD7713 with TFS
remaining low for the duration of the write operation. A0
determines whether a write operation transfers data to the con-
trol register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7713
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7713 on the high level of this
SCLK signal with the MSB transferred first. On the last active
high time of SCLK, the LSB is loaded to the AD7713.
Figure 13b shows a timing diagram for a write operation to the
AD7713 with TFS returning high during the write operation
and returning low again to write the rest of the data-word. Tim-
ing parameters and functions are very similar to that outlined
for Figure 13a, but Figure 13b has a number of additional times
to show timing relationships when TFS returns high in the
middle of transferring a word.
Data to be loaded to the AD7713 must be valid prior to the
rising edge of the SCLK signal. TFS should return high during
the low time of SCLK. After TFS returns low again, the next bit
of the data-word to be loaded to the AD7713 is clocked in on
REV. D
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation
( TFS Returns High During Write Operation)
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
SDATA (I)
SDATA (I)
SCLK (I)
SCLK (I)
TFS (I)
A0 (I)
TFS (I)
A0 (I)
t
32
t
32
MSB
MSB
t
t
26
35
t
35
–21–
t
t
26
36
t
27
t
27
BIT N
the next high level of the SCLK input. On the last active high
time of the SCLK input, the LSB is loaded to the AD7713.
SIMPLIFYING THE EXTERNAL CLOCKING MODE
INTERFACE
In many applications, the user may not require the facility of
writing to the on-chip calibration registers. In this case, the
serial interface to the AD7713 in external clocking mode can be
simplified by connecting the TFS line to the A0 input of the
AD7713 (see Figure 14). This means that any write to the
device will load data to the control register (since A0 is low
while TFS is low), and any read to the device will access data
from the output data register or from the calibration registers
(since A0 is high while RFS is low). It should be noted that in
this arrangement, the user does not have the capability of read-
ing from the control register. Another method of simplifying the
interface is to generate the TFS signal from an inverted RFS
signal. However, generating the signals the opposite way around
(RFS from an inverted TFS) will cause writing errors.
Figure 14. Simplified Interface with TFS Connected to A0
t
36
INTERFACE
t
30
LINES
FOUR
t
35
BIT N+1
LSB
t
34
t
36
RFS
SDATA
SCLK
TFS
A0
t
33
AD7713
AD7713