AD7718BR Analog Devices Inc, AD7718BR Datasheet - Page 19

• Manufacturer Part Number: AD7718BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7718BR

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Analog Front End For Low Frequency Measurement
• No. Of Channels: 10
• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 1.37k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.84mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7718EBZ - BOARD EVALUATION FOR AD7718
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SIGNAL CHAIN OVERVIEW CHOP DISABLED
(CHOP = 1)
With CHOP =1 chopping is disabled. With chopping disabled
the available output rates vary from 16.06 Hz (62.26 ms) to
1365.33 Hz (0.73 ms). The range of applicable SF words is from
3 to 255. When switching between channels with chop disabled,
the channel throughput is increased by a factor of two over the
case where chop is enabled. When used in multiplexed applica-
tions operation with chop disabled will offer the best throughput
time when cycling through all channels. The drawback with
chop disabled is that the drift performance is degraded and
calibration is required following a gain change or significant
temperature change. A block diagram of the ADC input
channel with chop disabled is shown in Figure 10. The
signal chain includes a mux, buffer, PGA, sigma-delta modu-
lator, and digital filter. The modulator bit stream is applied to
a Sinc
factor is restricted to an 8-bit register SF, the actual decima-
tion factor is the register value times 8. The decimated output
rate from the Sinc
fore be:
where
f
SF is the decimal equivalent of the word loaded to the filter
register, valid range is from 3 to 255,
f
The settling time to a step input is governed by the digital filter.
A synchronized step change will require a settling time of three
times the programmed update rate, a channel change can be
treated as a synchronized step change. An unsynchronized step
change will require four outputs to reflect the new analog input
at its output.
The allowable range for SF is 3 to 255 with a default of 69
(45H). The corresponding conversion rates, conversion times,
and settling times are shown in Table VI. Note that the conver-
sion time increases by 0.245 ms for each increment in SF.
ADC
MOD
is the ADC conversion rate,
is the modulator sampling rate of 32.768 kHz.
3
filter. The programming of the Sinc
3
filter (and the ADC conversion rate) will there-
t
SETTLE
f
ADC
=
ANALOG
f
INPUT
=
ADC
3
8
f
×
MOD
= ×
SF
3
MUX
t
ADC
3
decimation
BUF
PGA
f
IN
SF
Word
03
68
69 (Default)
75
82
151
255
The frequency response of the digital filter H (f) is as follows:
where
f
SF = value programmed into SF SFR.
The following shows plots of the filter frequency response using
different SF words for output data rates of 16 Hz to 1.36 kHz.
There are sinc
The 3 dB frequency for all values of SF obeys the following
equation:
The following plots show frequency response of the AD7708/
AD7718 digital filter for various filter words. The AD7708/
AD7718 are targeted at multiplexed applications. One of the
key requirements in these applications is to optimize the SF
word to obtain the maximum filter rejection at 50 Hz and 60 Hz
while minimizing the channel throughput rate. Figure 12 shows
the AD7708/AD7718 optimized throughput while maximizing
50 Hz and 60 Hz rejection. This is achieved with an SF word of
75. In Figure 13, by using a higher SF word of 151, 50 Hz and
60 Hz rejection can be maximized at 60 dB with a channel
throughput rate of 110 ms. An SF word of 255 gives maximum
rejection at both 50 Hz and 60 Hz but the channel throughput
rate is restricted to 186 ms as shown in Figure 14.
MOD
MOD0
Table VI. ADC Conversion and Settling Times for Various
SF Words with CHOP = 1
f
MOD
-
= 32,768 Hz,



SF
SINC
3
notches at integer multiples of the update rate.
1
×
3
FILTER
8
Data Update Rate
f
1365.33
60.2
59.36
54.6
49.95
27.13
16.06
f (3 dB) = 0.262 × f
×
ADC
sin(
(Hz)
f
ADC
SF
sin(
DIGITAL
OUTPUT
× ×
π
8
AD7708/AD7718
×
π
f f
/
×
MOD
ADC
f f
/
)
MOD
)
Settling Time
t
2.20
49.8
50.54
54.93
60
110.6
186.76
SETTLE



3
(ms)