AD7718BRUZ-REEL7 Analog Devices Inc, AD7718BRUZ-REEL7 Datasheet - Page 26

• Manufacturer Part Number: AD7718BRUZ-REEL7
• Description: 4/5 Chnl Dif Or 8/10 Chnl 24-Bit ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7718BRUZ-REEL7

• Number Of Bits: 24
• Sampling Rate (per Second): 1.37k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.84mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7718EBZ - BOARD EVALUATION FOR AD7718
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7718BRUZ-REEL7; AD7718BRUZ-REEL7TR

Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On-Reset = 00Hex)
The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register selecting the next operation to be a read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations
for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the
first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
Bit
Location
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
AD7708/AD7718
R
D
S 7
Y
R
(
) 0
Bit
Mnemonic Description
RDY
0
CAL
0
ERR
0
0
LOCK
0
S
R
(
) 0
6
Ready Bit for the ADC
Set when data is transferred to the ADC data registers or on completion of calibration cycle. The RDY
bit is cleared automatically a period of time before the data register is updated with a new conversion
result or after the ADC data register has been read. This bit is also cleared by a write to the mode bits to
indicate a conversion or calibration. The RDY pin is the complement of the RDY bit.
Bit is automatically cleared. Reserved for future use
Calibration Status Bit
Set to indicate completion of calibration. It is set at the same time that the RDY is set high.
Cleared by a write to the mode bits to start another ADC conversion or calibration.
This bit is automatically cleared. Reserved for future use
ADC Error Bit
Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.
After a calibration this bit also flags error conditions that caused the calibration registers not to be
written. Error sources include Overrange.
Cleared by a write to the mode bits to initiate a conversion or calibration.
This bit is automatically cleared. Reserved for future use
This bit is automatically cleared. Reserved for future use
PLL Lock Status Bit.
Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about
exact sampling frequencies etc., the LOCK bit should be interrogated and the result discarded if the
LOCK bit is zero.
C
A
S
L
R
5
(
) 0
Table XIV. Status Register Bit Designations
0
S
R
(
) 0
4
E
R
S
R
R
3
(
) 0
0
S
R
(
) 0
2
0
S
R
(
) 0
1
L
O
S
C
R
K
0
(
) 0