AD7781CRUZ Analog Devices Inc, AD7781CRUZ Datasheet - Page 13

• Manufacturer Part Number: AD7781CRUZ
• Description: 1CHANNEL L/POWER 20-BIT SD GAIN 128 IC
• Manufacturer: Analog Devices Inc

Specifications of AD7781CRUZ

• Design Resources: Weigh Scale Design Using AD7781 with Internal PGA (CN0108)
• Number Of Bits: 20
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL INTERFACE
The serial interface of the AD7781 consists of two signals: SCLK
and DOUT/ RDY . SCLK is the serial clock input for the device,
and data transfers occur with respect to the SCLK signal. The
DOUT/ RDY pin is dual purpose: it functions as a data ready
pin and as a data output pin. DOUT/ RDY goes low when a new
data-word is available in the output register. A 32-bit word is
placed on the DOUT/ RDY pin when sufficient SCLK pulses are
applied. This word consists of a 20-bit conversion result followed
by four 0s to generate a 24-bit word. Following this, status bits
are output.
the status bits and their functions.
DOUT/ RDY is reset high when the conversion has been read.
If the conversion is not read, DOUT/ RDY goes high prior to the
data register update to indicate when not to read from the device.
This ensures that a read operation is not attempted while the reg-
ister is being updated. Each conversion can be read only once. The
data register is updated for every conversion.
Table 9. Status Bit Functions
Bit Name
RDY
FILTER
ERR
ID1, ID0
GAIN
PAT1, PAT0
RDY
Figure 22
FILTER
Description
Ready bit.
0: a conversion is available.
Filter bit.
1: 10 Hz filter is selected.
0: 16.7 Hz filter is selected.
Error bit.
1: an error occurred during conversion. (An error occurs when the analog input is out of range.)
ID bits.
ID1
0
Gain bit.
1: gain = 1.
0: gain = 128.
Status pattern bits. When the user reads data from the AD7781, a pattern check can be performed.
PAT1
0
0
1
ERR
shows the status bits, and
Figure 22. Status Bits
ID1
ID0
0
PAT0
1
0
x
ID0
GAIN
PAT1
Table 9
Function
Indicates the ID number for the AD7781.
Function
Indicates that the serial transfer from the ADC was performed correctly (default).
Indicates that the serial transfer from the ADC was not performed correctly.
Indicates that the serial transfer from the ADC was not performed correctly.
PAT0
describes
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When a conversion is complete, the serial interface is reset, and
the new conversion is placed in the data register. Therefore, the
user must ensure that the complete word is read before the next
conversion is complete.
When PDRST is low, the DOUT/ RDY pin is tristated. When
PDRST is taken high, the internal clock requires approximately
1 ms to power up. Following power-up, the ADC continuously
converts. The first conversion requires the total settling time
(see
high and returns low only when a conversion is available. The
ADC then converts continuously, and subsequent conversions
are available at the selected update rate.
timing for a read operation from the AD7781.
When the filter response is changed (using the FILTER pin) or
the gain is changed (using the GAIN pin), the modulator and
filter are reset immediately (see Figure 5). DOUT/ RDY is set
high. The ADC then begins conversions using the selected filter
response/gain setting. DOUT/ RDY remains high until the appro-
priate settling time for that filter has elapsed. Therefore, the user
should complete any read operations before changing the gain or
update rate. Otherwise, 1s are read back from the AD7781 because
the DOUT/ RDY pin is set high following the gain/filter change.
Figure 4
). DOUT/
RDY goes high when PDRST is taken
Figure 3
shows the
AD7781