AD7781CRUZ Analog Devices Inc, AD7781CRUZ Datasheet - Page 5

• Manufacturer Part Number: AD7781CRUZ
• Description: 1CHANNEL L/POWER 20-BIT SD GAIN 128 IC
• Manufacturer: Analog Devices Inc

Specifications of AD7781CRUZ

• Design Resources: Weigh Scale Design Using AD7781 with Internal PGA (CN0108)
• Number Of Bits: 20
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
AV
Table 3.
Parameter
Read
Reset
1
2
3
4
5
Circuit and Timing Diagrams
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 3.
The values of t
SCLK active edge is falling edge of SCLK.
The PDRST high to data valid delay is typically 1 ms longer than t
DOUT/RDY
t
t
t
t
t
t
(OUTPUT)
DD
1
2
3
4
5
6
3
5
(INPUT)
2
= 2.7 V to 5.25 V, DV
SCLK
OUTPUT
1
3
Figure 2. Load Circuit for Timing Characterization
PIN
are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the V
TO
50pF
Figure 3. Read Cycle Timing Diagram
Limit at T
100
100
0
60
80
10
130
100
120
300
MSB
DD
t
3
t
= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
I
100µA WITH DV
I
100µA WITH DV
1
SINK
SOURCE
(1.6mA WITH DV
MIN
t
2
(200µA WITH DV
, T
1.6V
MAX
DD
DD
= 3V)
= 3V)
t
LSB
DD
4
= 5V,
DD
= 5V,
6
because the internal oscillator requires time to power up and settle.
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ms typ
ms typ
Rev. 0 | Page 5 of 16
GAIN OR FILTER
Test Conditions/Comments
SCLK high pulse width
SCLK low pulse width
SCLK active edge to data valid delay
DV
DV
SCLK inactive edge to DOUT/RDY high
PDRST low pulse width
FILTER/GAIN change to data valid delay
Update rate = 16.7 Hz
Update rate = 10 Hz
DOUT/RDY
(OUTPUT)
DD
DD
R
DOUT/RDY
(INPUT)
PDRST
(OUTPUT)
= t
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
(INPUT)
F
= 5 ns (10% to 90% of DV
Figure 5. Changing Gain or Filter Option
t
Figure 4. Resetting the AD7781
5
DD
, unless otherwise noted.
DD
t
6
) and timed from a voltage level of 1.6 V.
OL
or V
4
OH
limits.
AD7781