AD7813YRZ-REEL Analog Devices Inc, AD7813YRZ-REEL Datasheet - Page 6

• Manufacturer Part Number: AD7813YRZ-REEL
• Description: 10 BIT, SINGLE, PARALLEL,ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7813YRZ-REEL

• Number Of Bits: 10
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7813
CIRCUIT DESCRIPTION
Converter Operation
The AD7813 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to V
ures 2 and 3 below show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on V
When the ADC starts a conversion (see Figure 3), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The Control Logic and the Charge
Redistribution DAC are used to add and subtract fixed amounts
of charge from the sampling capacitor so as to bring the compara-
tor back into a balanced condition. When the comparator is
rebalanced the conversion is complete. The Control Logic gen-
erates the ADC output code. Figure 7 shows the ADC transfer
function.
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7813. The
parallel interface is implemented using an 8-bit data bus, the
falling edge of CONVST brings the BUSY signal high, and at
the end of conversion the falling edge of BUSY is used to ini-
tiate an Interrupt Service Routine (ISR) on a microprocessor—
see Parallel Interface section for more details. V
to a well decoupled V
0 V to V
up in a low current mode, i.e., power-down. A rising edge on an
internal CONVST input will cause the part to power up—see
Power-Up Times. If power consumption is of concern, the
automatic power-down at the end of a conversion should be
used to improve power performance. See Power vs. Throughput
Rate section of the data sheet.
AGND
AGND
V
V
IN
IN
+
+
DD
SW1
SW1
. When V
IN+
A
A
.
Figure 3. ADC Conversion Phase
B
B
CAPACITOR
SAMPLING
Figure 2. ADC Track Phase
CAPACITOR
SAMPLING
ACQUISITION
CONVERSION
V
V
DD
PHASE
PHASE
DD
DD
DD
/3
/3
is first connected the AD7813 powers
pin to provide an analog input range of
SW2
SW2
COMPARATOR
COMPARATOR
REDISTRIBUTION
REDISTRIBUTION
REF
CHARGE
CONTROL
CHARGE
CONTROL
CLOCK
is connected
DAC
LOGIC
CLOCK
DAC
LOGIC
OSC
OSC
DD
. Fig-
–6–
Analog Input
Figure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7813. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2,
in Figure 5, is typically about 4 pF and can be primarily attrib-
uted to pin capacitance. The resistor R1 is a lumped component
made up of the on resistance of a multiplexer and a switch. This
resistor is typically about 125 Ω. The capacitor C1 is the ADC
sampling capacitor and has a capacitance of 3.5 pF.
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on V
time; therefore, the minimum acquisition time needed is
approximately 100 ns.
Figure 6 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R2 repre-
sents the source impedance of a buffer amplifier or resistive
network, R1 is an internal multiplexer resistance and C1 is the
sampling capacitor.
2.7V TO 5.5V
SUPPLY
V
IN
4pF
Figure 5. Equivalent Analog Input Circuit
C2
Figure 4. Typical Connection Diagram
Figure 6. Equivalent Sampling Circuit
0V TO V
10 F
INPUT
REF
V
DD
R2
0.1 F
D1
D2
IN
CONVERT PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
is also being acquired during this settling
V
GND
V
IN
IN
V
125
AD7813
DD
R1
V
CONVST
3.5pF
DB0-DB7
REF
C1
BUSY
125
R1
RD
CS
3.5pF
C1
INTERFACE
V
PARALLEL
DD
/3
REV. C
C/ P