AD7914BRUZ Analog Devices Inc, AD7914BRUZ Datasheet - Page 8

• Manufacturer Part Number: AD7914BRUZ
• Description: 10-Bit 4,CH 1 Msps ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7914BRUZ

• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 13.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD79X4CBZ - BOARD EVALUATION FOR AD79X4CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7904/AD7914/AD7924
TIMING SPECIFICATIONS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 × V
t
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
11
12
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
8
3
3
4
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
2
Limit at T
V
10
20
16 × t
50
10
35
40
0.4 × t
0.4 × t
10
15/45
10
5
20
1
DD
= 3 V
SCLK
SCLK
SCLK
MIN
, T
MAX
V
10
20
16 × t
50
10
30
40
0.4 × t
0.4 × t
10
15/35
10
5
20
1
DD
1
AD7904/AD7914/AD7924
(V
= 5 V
SCLK
SCLK
SCLK
DD
= 2.7 V to 5.25 V, V
ns min/max
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
µs max
DRIVE
–8–
V
DD
, REF
SCLK Falling Edge to DOUT High Impedance
Description
Minimum Quiet Time Required Between CS Rising Edge
and Start of Next Conversion
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to DOUT Valid Hold Time
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/Auto
Shutdown Modes
IN
= 2.5 V, T
8
, quoted in the timing characteristics is the true bus relinquish
A
= T
DD
MIN
) and timed from a voltage level of 1.6 V.
DRIVE
to T
.
MAX
, unless otherwise noted.)
REV. 0