AD8432ACPZ-RL Analog Devices Inc, AD8432ACPZ-RL Datasheet - Page 18

• Manufacturer Part Number: AD8432ACPZ-RL
• Description: Dual Ultra Low Noise InAmp
• Manufacturer: Analog Devices Inc

Specifications of AD8432ACPZ-RL

• Amplifier Type: Voltage Feedback
• Number Of Circuits: 2
• Output Type: Differential
• Slew Rate: 295 V/µs
• -3db Bandwidth: 200MHz
• Voltage - Input Offset: 1000µV
• Current - Supply: 24mA
• Current - Output / Channel: 77mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Gain Bandwidth Product: -
• Current - Input Bias: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8432
THEORY OF OPERATION
LOW NOISE AMPLIFIER (LNA)
The AD8432 is a dual-channel, ultralow noise amplifier with
integrated pin-strappable, gain-setting resistors. The resistors
can be externally connected to achieve differential gains of
12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (×4, ×8, ×12, and
×16, respectively). A simplified schematic of an LNA is shown
in Figure 65.
The LNA is driven with a single-ended input and measured
differentially at the output. The inverting input INL must be
ac-coupled to ground through a capacitor for proper operation.
The LNA cannot be driven differentially due to the asymmetry
of the internal gain setting resistors. The gain from the inverting
input INL to the single-ended output (OPH or OPL) does not
match the gain from the noninverting input INH to the single-
ended output.
The AD8432 inputs have a dc bias voltage of 3.25 V, which is
generated internally. The inputs must be ac-coupled through a
series capacitor to maintain the dc bias level of the inputs. Likewise,
the AD8432 outputs have a dc bias voltage of 2.5 V. An ac coupling
capacitor in series with each single-ended output is recommended
to prevent improper loading of the outputs. The AD8432 inputs
have a dc bias voltage of 3.25 V, which is generated internally.
The inputs must be ac-coupled through a series capacitor to
maintain the dc bias level of the inputs (see CINL and CINH
in Figure 65).
The AD8432 supports a differential output voltage of 4.8 V p-p
for the common-mode output voltage of 2.5 V. Therefore, for a
R
S
V
S
C
R
SH
SH
GND
CINH
OPH
INH
RG4
48Ω
Figure 65. Simplified Schematic of LNA
GOH
RG3
24Ω
R
FB
Rev. B | Page 18 of 28
GMH
RG2
12Ω
VPS
Q1
I
I
differential gain of G = 12.04 dB, the maximum input voltage
allowed is 1.2 V p-p.
Clamping the inputs ensures quick recovery from large input
voltages. The input back-to-back diodes, which are integrated
inside the die (IND1 and IND2), should be used for the lowest gain
configuration (12.04 dB) to protect the input from overdriving.
They should be connected after the source resistance or before
the INH coupling capacitor.
The use of a fully differential topology and negative feedback
minimizes distortion. A differential signal enables smaller swings at
each output, which results in reduction of third-order distortion.
The AD8432 is a voltage feedback amplifier. Due to gain band-
width product (GBW), a decrease in bandwidth should be
expected as the gain increases. Table 5 displays the values of the
−3 dB bandwidth for each gain with unterminated input
impedance.
GAIN SETTING TECHNIQUE
Pin strapping is used to set the gain of the amplifier. Gain setting
resistors are integrated in the LNA and are accessible externally
through the GOH, GMH, GML, and GOL pins. By externally
shorting these pins, and thereby shorting or connecting the
internal resistors, the AD8432 can be configured for four different
gains. Table 5 shows which pins must be connected to achieve
the desired gain.
GND
RG1
12Ω
Q2
C
I
RG5
I
24Ω
FB
GML
RG6
24Ω
GOL
RG7
48Ω
GND
CINL
OPL
INL