AD9222BCPZ-40 Analog Devices Inc, AD9222BCPZ-40 Datasheet
AD9222BCPZ-40
Specifications of AD9222BCPZ-40
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AD9222BCPZ-40 Summary of contents
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FEATURES 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 ...
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AD9222 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications ...
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SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error ...
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AD9222 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz IN f ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter Temp CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage ...
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AD9222 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. 1 Parameter Temp Min CLOCK 2 Maximum Clock Rate Full 40 ...
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TIMING DIAGRAMS N – VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± ...
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AD9222 N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – FRAME t DATA LSB ...
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ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x ...
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AD9222 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN + G VIN – G VIN – H VIN + H DRGND DRVDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Table 7. Pin Function Descriptions Pin No. Mnemonic 0 ...
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Pin No. Mnemonic 33 D − SCLK/DTP 39 SDIO/ODM 40 CSB 41 PDWN 43 VIN + A 44 VIN − VIN − VIN + B 49 VIN + C 50 ...
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AD9222 EQUIVALENT CIRCUITS VIN ± x Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP AND PDWN Rev ...
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AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page AD9222 6kΩ ...
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AD9222 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.3 MHz, AD9222- AIN = –0.5dBFS SNR = 70.32dB ENOB ...
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AIN = –0.5dBFS SNR = 70.21dB –20 ENOB = 11.31 BITS SFDR = 82.37dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with f = 2.3 MHz, AD9222- ...
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AD9222 100 p-p, SFDR p-p, SNR ENCODE (MSPS) Figure 27. SNR/SFDR vs 2.3 MHz, AD9222-65 SAMPLE ...
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AIN1 AND AIN2 = –7dBFS SFDR = 89.87dB IMD2 = 96.07dBc –20 IMD3 = 90.16dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Two-Tone 32k FFT with MHz ...
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AD9222 90 85 SFDR 80 75 SNR ANALOG INPUT FREQUENCY (MHz) Figure 39. SNR/SFDR vs AD9222- p-p, SFDR p-p, SNR ...
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CODE Figure 45. INL 2.3 MHz, AD9222-50 IN 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 ...
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AD9222 2.5 2.0 1.5 1.0 0 – – – CODE Figure 51. Input-Referred Noise Histogram, AD9222-65 0 NPR = 60.3dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz –20 –40 –60 –80 –100 ...
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THEORY OF OPERATION The AD9222 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in ...
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AD9222 90 SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 1.0 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 55. SNR/SFDR vs. Common-Mode Voltage 2.3 MHz, AD9222- SFDR (dBc ...
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For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common- mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference ...
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AD9222 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9222 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins ...
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Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t ) can be calculated by A ...
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AD9222 By asserting the PDWN pin high, the AD9222 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9222 returns to ...
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An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 73 and Figure 74. ...
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AD9222 500 EYE: ALL BITS 400 300 200 100 0 –100 –200 –300 –400 –500 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 140 120 100 –300ps –200ps –100ps 0ps 100ps Figure 76. Data Eye for LVDS Outputs ...
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Two output clocks are provided to assist in capturing data from the AD9222. The DCO is used to clock the output data and is equal to six times the sample clock (CLK) rate. Data is clocked out of the AD9222 ...
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AD9222 When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in ...
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CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. ...
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AD9222 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 82 shows the typical drift characteristics of the internal reference in 1 ...
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SERIAL PORT INTERFACE (SPI) The AD9222 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization, depending on ...
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AD9222 HARDWARE INTERFACE The pins described in Table 14 compose the physical interface between the user’s programming device and the serial port of the AD9222. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin ...
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CSB SCLK DON’T CARE R A12 SDIO DON’T CARE Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns CLK ...
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AD9222 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), ...
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Table 16. Memory Map Register Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X Child ID [6:4] (identify device variants ...
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AD9222 Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 14 output_mode LVDS ANSI-644 (default LVDS low power, (IEEE 1596.3 similar) 15 output_adjust output_phase user_patt1_lsb user_patt1_msb ...
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Power and Ground Recommendations When connecting power to the AD9222 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed ...
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AD9222 EVALUATION BOARD The AD9222 evaluation board provides all of the support cir- cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default AD8334 driver. The ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9222 Rev. A evaluation board. • POWER: Connect the switching power supply that is provided with the evaluation ...
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AD9222 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this drive option is in use, some components may need to be populated, in which ...
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Figure 90. Evaluation Board Schematic, DUT Analog Inputs Rev Page AD9222 05967-072 ...
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AD9222 Figure 91. Evaluation Board Schematic, DUT Analog Inputs (Continued) Rev Page 05967-073 ...
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R302 DNP 49 VIN_C VIN+C 50 VIN−C VIN_C 51 AVDD AVDD_DUT 52 VIN−D VIN_D R301 53 VIN_D VIN+D 10kΩ 54 RBIAS 55 VSENSE_DUT SENSE 56 VREF VREF_DUT 57 REFB 58 REFT 59 AVDD_DUT AVDD 60 VIN_E VIN+E 61 VIN_E ...
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AD9222 GND RSET S10 6 VREF Figure 93. Evaluation Board Schematic, ...
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R524 R513 187Ω C512 C511 10µF 0.1µF C510 C509 10µF 0.1µF 49 VCM2 50 VCM1 R504 10kΩ 51 AVDD_5V EN34 R505 10kΩ 52 EN12 53 CLMP12 54 GAIN12 VG12 55 VPS1 AVDD_5V 56 VIN1 57 VIP1 58 LOP1 59 LON1 ...
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AD9222 C610 C609 10µF 0.1µF R605 AVDD_5V 10kΩ AVDD_5V C605 0.1µF R603 274Ω C602 0.018µF 0.1µF C601 AVDD_5V CW GND VG56 Variabl e Gain Circuit (0−1.0V DC) VG56 External Variable Gain Drive Figure 95. Evaluation Board Schematic, Optional DUT Analog ...
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CR702 GREEN R709 0Ω SDO_CHA 0Ω R708 SDI_CHA R707 0Ω SCLK_CHA R706 0Ω CSB1_CHA CR701 2 OPTIONAL GREEN Figure 96. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry C702 C703 0.1µF 0.1µF PICVCC 1 2 PICVCC GP1 3 ...
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AD9222 Figure 97. Evaluation Board Layout, Primary Side Rev Page ...
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Figure 98. Evaluation Board Layout, Ground Plane Rev Page AD9222 ...
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AD9222 Figure 99. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD9222 ...
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AD9222 Table 17. Evaluation Board Bill of Materials (BOM) Qnty. per Reference Board Designator Item Device 1 1 AD9222-65EBZ PCB 2 118 C101, C102, C107, Capacitor C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, ...
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Qnty. per Reference Item Board Designator Device 8 8 C503, C514, C520, Capacitor C526, C603, C614, C620, C626 9 1 C704 Capacitor 10 9 C307, C714, C715, Capacitor C716, C717, C719, C720, C721, C722 11 16 C540, C541, C544, Capacitor ...
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AD9222 Qnty. per Reference Item Board Designator Device 26 32 L505, L506, L507, Resistor L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, ...
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Qnty. per Reference Item Board Designator Device 37 8 R161, R162, R163, Resistor R164, R208, R225, R241, R259 38 3 R303, R305, R306 Resistor 39 1 R414 Resistor 40 1 R404 Resistor 41 1 R309 Resistor 42 5 R310, R501, ...
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... ADP33339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator CP-64-3 AD8334ACPZ-REEL, ultralow noise precision dual VGA SOT-223 ADP3339AKC-5-RL7 SOT-223 ADP3339AKC-3.3-RL CP-64-3 AD9222BCPZ-65, octal, 12-bit, 50 MSPS serial LVDS 1.8 V ADC SOT-23 ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference LFCSP AD9515BCPZ, 1.6 GHz CP-32-2 clock distribution IC ...
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OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9222ABCPZ-40 −40°C to +85°C AD9222ABCPZRL7-40 −40°C to +85°C AD9222ABCPZ-50 −40°C to +85°C AD9222ABCPZRL7-50 −40°C to +85°C AD9222ABCPZ-65 −40°C ...
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AD9222 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05967-0-4/10(D) Rev Page ...