AD9251BCPZ-40 Analog Devices Inc, AD9251BCPZ-40 Datasheet - Page 26

• Manufacturer Part Number: AD9251BCPZ-40
• Description: 14 BIT DUAL 40 Msps Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9251BCPZ-40

• Number Of Bits: 14
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 105.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9251
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
jitter (t
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 56.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9251.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
See the
Note available on
CHANNEL/CHIP SYNCHRONIZATION
The AD9251 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized
to the sample clock; however, to ensure there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the analog core power dissipated by
the AD9251 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
primarily by the strength of the digital drivers and the load
on each output bit.
SNR
JRMS
80
75
70
65
60
55
50
45
AN-501
1
HF
) can be calculated by
= −10 log[(2π × f
Figure 56. SNR vs. Input Frequency and Jitter
Application Note and the
www.analog.com
LF
) at a given input frequency (f
10
FREQUENCY (MHz)
INPUT
× t
for more information.
JRMS
)
100
AN-756
2
+ 10
3.0ps
(
−
SNR
Application
0.05ps
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
INPUT
LF
/
10
) due to
)
]
1k
Rev. A | Page 26 of 36
The maximum DRVDD current (IDRVDD) can be calculated as
where N is the number of output bits (30, in the case of the
AD9251).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 57 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
The AD9251 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2.2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the AD9251 to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
IDRVDD = V
150
130
110
90
70
50
0
Figure 57. Analog Core Power vs. Clock Rate
CLK
10
/2. In practice, the DRVDD current is estab-
DRVDD
AD9251-20
20
× C
CLOCK RATE (MSPS)
30
LOAD
AD9251-40
× f
40
CLK
AD9251-65
× N
50
60
AD9251-80
70
80