AD9252ABCPZ-50 Analog Devices Inc, AD9252ABCPZ-50 Datasheet
AD9252ABCPZ-50
Specifications of AD9252ABCPZ-50
Related parts for AD9252ABCPZ-50
AD9252ABCPZ-50 Summary of contents
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FEATURES 8 analog-to-digital converters (ADCs) integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.4 LSB ...
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AD9252 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications ...
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SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error ...
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AD9252 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz IN f ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input Voltage ...
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AD9252 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. 1 Parameter CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock ...
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TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± ...
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AD9252 N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – FRAME t DATA LSB ...
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ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x ...
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AD9252 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN + G VIN – G VIN – H VIN + H DRGND DRVDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Table 7. Pin Function Descriptions Pin No. Mnemonic 0 ...
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Pin No. Mnemonic − SCLK/DTP 39 SDIO/ODM 40 CSB 41 PDWN 43 VIN + A 44 VIN − VIN − VIN + B 49 ...
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AD9252 EQUIVALENT CIRCUITS VIN ± x Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP OR PDWN Rev ...
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AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page AD9252 6kΩ ...
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AD9252 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.3 MHz AIN = –0.5dBFS SNR = 72.98dB ENOB = 11.83 BITS ...
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SFDR 80dB REFERENCE 40 SNR –60 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) Figure 21. SNR/SFDR vs. Analog Input Level 10.3 MHz SFDR 70 60 ...
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AD9252 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 2000 4000 6000 8000 10000 12000 14000 CODE Figure 27. INL 2.3 MHz SAMPLE 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 ...
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THEORY OF OPERATION The AD9252 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the ...
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AD9252 For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference ...
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CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9252 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are ...
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AD9252 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t ) can be calculated by ...
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By asserting the PDWN pin high, the AD9252 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9252 returns to normal ...
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AD9252 500 EYE: ALL BITS 400 300 200 100 0 –100 –200 –300 –400 –500 –1.5ns –1.0ns –0.5ns 0ns 0.5ns –150ps –100ps –50ps 0ps 50ps Figure 48. Data Eye for ...
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Two output clocks are provided to assist in capturing data from the AD9252. The DCO is used to clock the output data and is equal to seven times the sample clock (CLK) rate. Data is clocked out of the AD9252 ...
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AD9252 When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in ...
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CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. ...
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AD9252 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 54 shows the typical drift characteristics of the internal reference in 1 ...
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SERIAL PORT INTERFACE (SPI) The AD9252 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, ...
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AD9252 CSB SCLK DON’T CARE R A12 SDIO DON’T CARE Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns CLK ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the ...
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AD9252 1 Table 16. Memory Map Register Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X Child ID [6:4] (identify ...
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Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 14 output_mode LVDS ANSI-644 (default LVDS low power, (IEEE 1596.3 similar) 15 output_adjust output_phase user_patt1_lsb user_patt1_msb B15 ...
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AD9252 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9252 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. ...
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EVALUATION BOARD The AD9252 evaluation board provides all the support cir- cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially by using a transformer (default AD8334 driver. The ADC ...
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AD9252 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9252 Rev. A evaluation board. • Power: Connect the switching power supply that is provided with the ...
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ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this drive option is in use, some components may need to be populated, in which case ...
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AD9252 Figure 62. Evaluation Board Schematic, DUT Analog Inputs Rev Page 06296-072 ...
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Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued) Rev Page AD9252 06296-073 ...
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AD9252 49 VIN+C VIN_C 50 VIN−C VIN_C 51 AVDD_DUT AVDD 52 VIN−D VIN_D 53 R301 VIN_D VIN+D 10kΩ 54 RBIAS 55 VSENSE_DUT SENSE 56 VREF_DUT VREF 57 REFB 58 REFT 59 AVDD_DUT AVDD 60 VIN_E VIN+E 61 VIN−E VIN_E 62 ...
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GND RSET S10 6 VREF Figure 65. Evaluation Board Schematic, Clock ...
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AD9252 C510 C509 10µF 0.1µF AVDD_5V R505 10kΩ AVDD_5V C505 0.1µF R503 274Ω C502 0.018µF 0.1µF C501 AVDD_5V CW GND VG12 Variable Gain Circuit (0−1.0V DC) VG12 External Variable Gain Drive Figure 66. Evaluation Board Schematic, Optional DUT Analog Input ...
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R613 187Ω C612 C611 10µF 0.1µF C610 C609 10µF 0.1µF VCM2 49 VCM1 50 R604 10kΩ R605 AVDD_5V EN34 10kΩ 51 EN12 52 CLMP12 53 VG56 GAIN12 54 AVDD_5V VPS1 55 VIN1 56 VIP1 57 LOP1 58 LON1 59 COM1X ...
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AD9252 CR702 GREEN R709 0Ω SDO_CHA 0Ω R708 SDI_CHA R707 0Ω SCLK_CHA R706 0Ω CSB1_CHA 2 Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry C702 C703 0.1µF 0.1µF PICVCC 1 2 PICVCC GP1 3 4 GP1 ...
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Figure 69. Evaluation Board Layout, Primary Side Rev Page AD9252 ...
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AD9252 Figure 70. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 71. Evaluation Board Layout, Power Plane Rev Page AD9252 ...
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AD9252 Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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Table 17. Evaluation Board Bill of Materials (BOM) Qty per Reference Board Designator Item 1 1 AD9252LFCSP_REVA 2 118 C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, ...
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AD9252 Qty per Reference Item Board Designator 8 8 C503, C514, C520, C526, C603, C614, C620, C626 9 1 C704 10 9 C307, C714, C715, C716, C717, C719, C720, C721, C722 11 16 C540, C541, C544, C545, C548, C549, C552, ...
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Qty per Reference Item Board Designator 26 32 L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 ...
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AD9252 Qty per Reference Item Board Designator 37 8 R161, R162, R163, R164, R208, R225, R241, R259 38 3 R303, R305, R306 39 1 R414 40 1 R404 41 1 R309 42 5 R310, R501, R535, R601, R634 43 1 ...
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Qty per Reference Item Board Designator 55 9 T101, T102, T103, T104, T201, T202, T203, T204, T401 56 2 U704, U707 57 2 U501, U601 58 1 U706 59 1 U705 60 1 U301 61 1 U302 62 1 U401 ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9252ABCPZ-50 −40°C to +85°C AD9252ABCPZRL7-50 −40°C to +85°C AD9252-50EBZ RoHS Compliant Part. ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...