AD9259ABCPZ-50 Analog Devices Inc, AD9259ABCPZ-50 Datasheet
AD9259ABCPZ-50
Specifications of AD9259ABCPZ-50
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AD9259ABCPZ-50 Summary of contents
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FEATURES 4 ADCs integrated into 1 package 98 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.5 LSB (typical) INL ...
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AD9259 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications ...
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REVISION HISTORY 4/10—Rev Rev. D Changes to Table 16 ........................................................................ 33 Updated Outline Dimensions ........................................................ 51 Changes to Ordering Guide ........................................................... 51 11/09—Rev Rev. C Added EPAD Note to Figure 5 ...................................................... 11 Changes to Input ...
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AD9259 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain ...
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AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz ...
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AD9259 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input ...
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SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table Parameter CLOCK 3 Maximum Clock Rate Minimum Clock Rate Clock ...
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AD9259 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± ...
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N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – FRAME t DATA LSB ...
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AD9259 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD 1 Digital Outputs to DRGND CLK+, CLK− to AGND VIN + x, VIN – AGND SDIO/ODM to AGND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD AVDD VIN – D VIN + D AVDD AVDD CLK– CLK+ AVDD AVDD DRGND DRVDD NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. ...
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AD9259 Pin No. Mnemonic 30 CSB 31 PDWN 33 VIN + A 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN ...
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EQUIVALENT CIRCUITS VIN ± x Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V AND PDWN Rev Page 13 ...
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AD9259 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page 6kΩ ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.4 MHz AIN = –0.5dBFS SNR = 72.94dB ENOB = 11.82 BITS –20 ...
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AD9259 90 2V p-p, SFDR p-p, SNR ENCODE (MSPS) Figure 21. SNR/SFDR vs. Encode 10.3 MHz p-p, SFDR ...
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SFDR (dBc p-p, SNR (dB 100 ANALOG INPUT FREQUENCY (MHz) Figure 27. SNR/SFDR vs. Analog Input Frequency p-p, SFDR ...
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AD9259 0 NPR = 63.89dB NOTCH = 18.0MHz –20 NOTCH WIDTH = 3.0MHz –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Noise Power Ratio (NPR MSPS Figure 34. Full-Power Bandwidth ...
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THEORY OF OPERATION The AD9259 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in ...
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AD9259 For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common- mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal ...
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CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9259 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are ...
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AD9259 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f due only to aperture jitter (t ) can be calculated by J ...
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By asserting the PDWN pin high, the AD9259 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI ...
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AD9259 EYE: ALL BITS 500 0 0 –500 –1.0ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far ...
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Two output clocks are provided to assist in capturing data from the AD9259. The DCO is used to clock the output data and is equal to seven times the sample clock (CLK) rate. Data is clocked out of the AD9259 ...
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AD9259 When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in ...
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SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power- up. When ...
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AD9259 Internal Reference Operation A comparator within the AD9259 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 53), setting VREF ...
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SERIAL PORT INTERFACE (SPI) The AD9259 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and customization, ...
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AD9259 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 57. SDIO Pin Loading ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the ...
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AD9259 Table 16. Memory Map Register Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X Child ID [6:4] (identify device ...
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Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 14 output_mode LVDS ANSI-644 (default LVDS low power (IEEE 1596.3 similar) 15 output_adjust output_phase user_patt1_lsb user_patt1_msb B15 ...
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AD9259 Power and Ground Recommendations When connecting power to the AD9259 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be ...
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EVALUATION BOARD The AD9259 evaluation board provides all of the support cir- cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default AD8332 driver. The ADC ...
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AD9259 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9259 Rev. A evaluation board. • POWER: Connect the switching power supply that is provided in the ...
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ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which case ...
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AD9259 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 DNP AIN R102 64.9Ω VGA INPUT CONNECTION CHANNEL B P103 AIN P106 DNP VGA INPUT CONNECTION INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω AVDD_DUT VGA INPUT ...
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AVDD_DUT V– DNP - 100kΩ R267 DNP - 100kΩ R266 B – VIN VIN_B VIN VIN_B 38 AVDD_DUT AVDD 39 RBIAS 40 SENSE VSENSE_DUT 41 VREF VREF_DUT 42 REFB 43 REFT 44 AVDD_DUT AVDD ...
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AD9259 POPULATE L301 TO L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. R312 10kΩ R313 10kΩ DNP C311 0.1µF C312 0.1µF R315 C315 10kΩ 10µF DNP: DO NOT POPULATE Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive ...
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SDO_CHA 0Ω R427 SDI_CHA 0Ω R420 SCLK_CHA 0Ω R428 CSB1_CHA 0Ω R426 ±75mV = H = PIN ±50mV = LO = PIN PIN RCLAMP AVDD_5V FILTER. OWN YOUR DESIGN OR RESISTORS 0Ω WITH L408 TO L401 POPULATE CH_A CH_A AVDD_5V ...
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AD9259 Figure 66. Evaluation Board Schematic, Power Supply Inputs Rev Page GND GND 1 1 GND GND 1 1 ...
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Figure 67. Evaluation Board Layout, Primary Side Rev Page AD9259 ...
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AD9259 Figure 68. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 69. Evaluation Board Layout, Power Plane Rev Page AD9259 ...
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AD9259 Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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Table 17. Evaluation Board Bill of Materials (BOM) Item Qty. Reference Designator 1 1 AD9259LFCSP_REVA 2 75 C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, ...
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AD9259 Item Qty. Reference Designator 17 1 F501 18 1 FER501 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 4 J201 to J204 23 1 J401 ...
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Item Qty. Reference Designator 35 15 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 36 8 R108, R110, R121, R122, R134, R136, R146, R147 37 4 R161, R162, R163, R164 38 3 R202, ...
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AD9259 Item Qty. Reference Designator 57 2 U301, U401 58 1 U504 59 1 U502 60 1 U201 61 1 U203 62 1 U202 63 1 U403 64 1 U404 65 1 U402 1 This BOM is RoHS compliant. Device ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9259ABCPZ-50 −40°C to +85°C AD9259ABCPZRL7-50 −40°C to +85°C AD9259-50EBZ RoHS Compliant Part. 7.10 0.60 MAX 7.00 SQ 6.90 0.60 MAX 0.50 6.85 REF 6 ...
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AD9259 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05965-0-4/10(D) Rev Page ...