AD9281ARS Analog Devices Inc, AD9281ARS Datasheet - Page 3

• Manufacturer Part Number: AD9281ARS
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD9281ARS

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package / Case: 28-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 8
• Sampling Rate (per Second): 28M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 260mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REV. F
Parameter
DYNAMIC PERFORMANCE (SE)
DIGITAL INPUTS
LOGIC OUTPUT (with DVDD = 3 V)
LOGIC OUTPUT (with DVDD = 5 V)
CLOCKING
NOTES
1
2
3
Specifications subject to change without notice.
SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.
AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.
IMD referred to larger of two input signals.
Signal-to-Noise and Distortion
Signal-to-Noise
Total Harmonic Distortion
Spurious Free Dynamic Range
High Input Voltage
Low Input Voltage
DC Leakage Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
Data Valid Delay
MUX Select Delay
Data Enable Delay
Data High-Z Delay
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
f = 3.58 MHz
f = 3.58 MHz
f = 3.58 MHz
f = 3.58 MHz
(I
(I
(I
(I
OH
OL
OH
OL
= 1.5 mA)
= 1.5 mA)
= 50 A)
= 50 A)
OUTPUT
SELECT
CLOCK
INPUT
INPUT
DATA
t
OD
ADC SAMPLE
#1
1
SAMPLE #1-3
Q CHANNEL
OUTPUT
OUTPUT ENABLED
Q CHANNEL
Symbol
SINAD
SNR
THD
SFDR
V
V
I
C
V
V
V
V
t
t
t
t
t
t
IN
OD
MD
ED
DHZ
CH
CL
IH
IL
OH
OL
OH
OL
IN
ADC SAMPLE
#2
SAMPLE #1-2
Q CHANNEL
OUTPUT
Figure 1. ADC Timing
SAMPLE #1-1
Q CHANNEL
Min
2.4
16.9
16.9
ADC SAMPLE
#3
OUTPUT
t
–3–
MD
Typ
47.2
48
–55
–58
± 6
2
2.88
0.095
4.5
0.4
11
7
13
13
3.0
SAMPLE #1-1
I CHANNEL
OUTPUT
Max
0.3
ADC SAMPLE
#4
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #1
I CHANNEL
OUTPUT
Units
dB
dB
dB
dB
V
V
pF
V
V
V
V
ns
ns
ns
ns
ns
ns
Cycles
A
ADC SAMPLE
#5
I CHANNEL
OUTPUT ENABLED
SAMPLE #2
Q CHANNEL
OUTPUT
Condition
C
90% of Final Value
L
= 20 pF. Output Level to
AD9281