AD9281ARS Analog Devices Inc, AD9281ARS Datasheet - Page 4

• Manufacturer Part Number: AD9281ARS
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD9281ARS

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package / Case: 28-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 8
• Sampling Rate (per Second): 28M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 260mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9281
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
DVDD
AVSS
AVDD
CLK
Digital Outputs
AINA, AINB
VREF
REFSENSE
REFT, REFB
Junction Temperature
Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9281 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
10 sec
(MSB) D7
(LSB) D0
SELECT
CLOCK
DVDD
DNC
DNC
DVSS
PIN CONFIGURATION
D1
D2
D3
D4
D5
D6
With
Respect
to
AVSS
DVSS
DVSS
DVDD
AVSS
DVSS
AVSS
AVSS
AVSS
AVSS
NC = NO CONNECT
(Not to Scale)
TOP VIEW
AD9281
–6.5
–0.3
–0.3
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–1.0
–0.3
–65
CHIP-SELECT
INA-Q
INB-Q
REFT-Q
REFB-Q
AVDD
VREF
REFSENSE
AVSS
REFB-I
REFT-I
INB-I
INA-I
SLEEP
Max
+6.5
+6.5
+0.3
+6.5
AVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+150
+300
+150
Units
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
–4–
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSBs beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
P
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
in
Name
DVSS
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
SELECT
CLOCK
SLEEP
INA-I
INB-I
REFT-I
REFB-I
AVSS
REFSENSE
VREF
AVDD
REFB-Q
REFT-Q
INB-Q
INA-Q
CHIP-SELECT Hi-High Impedance, Lo-Normal Operation
DNC
DNC
PIN FUNCTION DESCRIPTIONS
Description
Digital Ground
Digital Supply
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (MSB)
Hi I Channel Out, Lo Q Channel Out
Clock
Hi Power Down, Lo Normal Operation
I Channel, A Input
I Channel, B Input
Top Reference Decoupling, I Channel
Bottom Reference Decoupling, I Channel
Analog Ground
Reference Select
Internal Reference Output
Analog Supply
Bottom Reference Decoupling, Q Channel
Top Reference Decoupling, Q Channel
Q Channel B Input
Q Channel A Input
Do not connect
Do not connect
WARNING!
ESD SENSITIVE DEVICE
REV. F