AD9380KSTZ-150 Analog Devices Inc, AD9380KSTZ-150 Datasheet - Page 14

• Manufacturer Part Number: AD9380KSTZ-150
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

AD9380
For more detail on setting the SOG threshold and other SOG-
related functions, see the Sync Processing section.
Clock Generation
A PLL is employed to generate the pixel clock. In this PLL,
the HSYNC input provides a reference frequency. A voltage
controlled oscillator (VCO) generates a much higher pixel clock
frequency. This pixel clock is divided by the PLL divide value
(Register 0x01 and Register 0x02) and phase compared with the
HSYNC input. Any error is used to shift the VCO frequency
and maintain lock between the two signals.
The stability of this clock is a very important element in provi-
ding the clearest and most stable image. During each pixel time,
there is a period during which the signal slews from the old
pixel amplitude and settles at its new value. This is followed by a
time when the input voltage is stable before the signal must slew
to a new value. The ratio of the slewing time to the stable time is
a function of the bandwidth of the graphics DAC and the
bandwidth of the transmission system (cable and termination).
It is also a function of the overall pixel rate. Clearly, if the
dynamic characteristics of the system remain fixed, then the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter and
the stable pixel time also becomes shorter.
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time. Considerable care has been taken in
the design of the AD9380 clock generation circuit to minimize
jitter. The clock jitter of the AD9380 is less than 13% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
Figure 4. Typical Clamp Configuration for RGB/YUV Applications
PIXEL CLOCK
Figure 5. Pixel Sampling Times
47nF
47nF
47nF
1nF
INVALID SAMPLE TIMES
R
B
G
SOG
AIN
AIN
AIN
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The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is shown in Figure 6. Recommended settings
of the VCO range and charge pump current for VESA standard
display modes are listed in Table 9.
Four programmable registers are provided to optimize the
performance of the PLL. These registers are:
•
•
•
The coast pin or the internal coast is used to allow the PLL to
continue to run at the same frequency, in the absence of the
incoming HSYNC signal or during disturbances in HSYNC
(such as equalization pulses). Coasting can be used during the
vertical sync period or any other time that the HSYNC signal is
unavailable. The polarity of the coast signal can be set through
the coast polarity register. Also, the polarity of the HSYNC
signal can be set through the HSYNC polarity register. For both
HSYNC and coast, a value of 1 is active high. The internal coast
function is driven off the VSYNC signal, which is typically a
time when HSYNC signals can be disrupted with extra
equalization pulses.
The 12-bit divisor register (R0x01, R0x02). The input
HSYNC frequency range can be any frequency which,
combined with the PLL_Div, does not exceed the VCO
range . The PLL multiplies the frequency of the HSYNC
signal, producing pixel clock frequencies in the range of
10 MHz to 100 MHz. The divisor register controls the
exact multiplication factor.
The 2-bit VCO range register (R0x03[7:6]). To improve the
noise performance of the AD9380, the VCO operating
frequency range is divided into four overlapping regions.
The VCO range register sets this operating range. The
frequency ranges for the lowest and highest regions are
shown in Table 7.
Table 7.
VCORNGE
00
01
10
11
The 5-bit phase adjust register (R0x04). The phase of the
generated sampling clock can be shifted to locate an
optimum sampling point within a clock cycle. The phase
adjust register provides 32 phase-shift steps of 11.25° each.
The HSYNC signal with an identical phase shift is available
through the HSOUT pin.
8nF
C
P
Figure 6. PLL Loop Filter Detail
FILT
1.5kΩ
R
Z
Pixel Rate Range
12 to 30
30 to 60
60 to 120
120 to 150
C
80nF
Z
PV
D