AD9518-2ABCPZ Analog Devices Inc, AD9518-2ABCPZ Datasheet - Page 59

• Manufacturer Part Number: AD9518-2ABCPZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9518-2ABCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.33GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.33GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex)
0x1E1
Table 48. System
Reg.
Addr.
(Hex)
0x230
Table 49. Update All Registers
Reg.
Addr
(Hex)
0x232
Bits
1
0
Bits
2
1
0
Bits
0
Name
Power down SYNC
Power down
distribution reference
Soft SYNC
Name
Update all registers
Name
Select VCO or CLK
Bypass VCO divider
Description
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Description
Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is,
it does not have to be set back to 0.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
Rev. A | Page 59 of 64
AD9518-2