AD9518-2ABCPZ Analog Devices Inc, AD9518-2ABCPZ Datasheet - Page 8

• Manufacturer Part Number: AD9518-2ABCPZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9518-2ABCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.33GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.33GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-2
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 2.21 GHz; LVPECL = 245.76 MHz; PLL LBW = 138 kHz
VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 138 kHz
VCO = 2.21 GHz; LVPECL = 61.44 MHz; PLL LBW = 138 kHz
VCO = 2.18 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz
VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Rev. A | Page 8 of 64
Min
Min
Min
515
570
Typ
Typ
54
77
109
79
114
163
124
176
259
Typ
146
329
151
329
203
376
Max
Max
Max
Unit
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Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup using an
external 245.76 MHz VCXO (Toyocom
TCO-2112);
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz