AD9520-2BCPZ-REEL7 Analog Devices Inc, AD9520-2BCPZ-REEL7 Datasheet - Page 44

• Manufacturer Part Number: AD9520-2BCPZ-REEL7
• Description: 12/24 Channel Clock Distribution W/ On-C
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-2BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.33GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.33GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-2
CLOCK DISTRIBUTION
A clock channel consists of three LVPECL clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVPECL or CMOS at the pins.
The AD9520 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer from
1 to 32.
The AD9520 features a VCO divider that divides the VCO output
by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz.
The other is to allow the AD9520 to generate even lower
frequencies than would be possible with only a simple post divider.
External clock signals connected to the CLK input can also use
the VCO divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For example, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
CLK
CLK
LF
MODE 0 (INTERNAL VCO MODE)
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
0
PLL
BUTION
DISTRI-
CLOCK
Figure 49. Simplified Diagram of the Three Clock Distribution Operation Modes
CLK
CLK
LF
MODE 1 (CLOCK DISTRIBUTION MODE)
Rev. 0 | Page 44 of 84
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
Operation Modes
There are three clock distribution operating modes, and these
are shown in Figure 49. One of these modes uses the internal
VCO, whereas the other two modes bypass the internal VCO
and use the signal provided on the CLK/ CLK pins.
In Mode 0 (internal VCO mode), there are two signal paths
available. In the first path, the VCO signal is sent to the VCO
divider and then to the individual channel dividers. In the
second path, the user bypasses the VCO and channel dividers
and sends the VCO signal directly to the drivers.
When CLK is selected as the source, it is not necessary to use the
VCO divider if the CLK frequency is less than the maximum
channel divider input frequency (1600 MHz); otherwise, the
VCO divider must be used to reduce the frequency going to
the channel dividers.
Table 31 shows how the VCO, CLK, and VCO divider are selected.
0x1E1[1:0] selects the channel divider source and determines
whether the VCO divider is used. It is not possible to select the
VCO without using the VCO divider.
Table 31. Operation Modes
Mode
2
1
0
CLK or VCO Direct-to-LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs. This configuration can pass frequencies
up to the maximum frequency of the VCO directly to the LVPECL
outputs. However, the LVPECL outputs may not be able to meet
the V
0
PLL
OD
BUTION
CLOCK
DISTRI-
specification in Table 4 at the highest frequencies.
[1]
0
0
1
1
0x1E1
[0]
0
1
0
1
CLK
CLK
LF
MODE 2 (HF CLOCK DISTRIBUTION MODE)
Channel Divider Source
CLK
CLK
VCO
Not allowed
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
0
PLL
VCO Divider
Used
Not used
Used
Not allowed
BUTION
CLOCK
DISTRI-