AD9520-4BCPZ-REEL7 Analog Devices Inc, AD9520-4BCPZ-REEL7 Datasheet - Page 39

• Manufacturer Part Number: AD9520-4BCPZ-REEL7
• Description: Clock IC With 1.6GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-4BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External VCXO/VCO Clock Input (CLK/ CLK )
This differential input is used to drive the AD9520 clock
distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased and the input signal should
be ac-coupled via capacitors.
The CLK/ CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the internal PLL, when the internal VCO is
not used. These inputs are also used as a feedback path for the
external zero delay mode.
Holdover
The AD9520 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This function is useful when the PLL reference clock is
lost. Holdover mode allows the VCO to maintain a relatively
constant frequency even though there is no reference clock.
Without this function, the charge pump is placed into a constant
pump-up or pump-down state, resulting in a massive VCO
frequency shift. Because the charge pump is placed in a high
impedance state, any leakage that occurs at the charge pump
output or the VCO tuning node causes a drift of the VCO
frequency. This can be mitigated by using a loop filter that
contains a large capacitive component because this drift is
limited by the current leakage induced slew rate (I
the VCO control voltage.
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the holdover
function must be enabled (0x01D[0]).
Note that the VCO cannot be calibrated with the holdover enabled
because the holdover resets the N divider during calibration,
which prevents proper calibration. Disable holdover before
issuing a VCO calibration.
CLK
CLK
VS
Figure 43. CLK Equivalent Input Circuit
2.5kΩ
5kΩ
5kΩ
2.5kΩ
CLOCK INPUT
STAGE
LEAK
/C) of
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Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state if there is no
reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, the channel dividers should be set to
ignore the SYNC pin (at least after an initial SYNC event). If the
dividers are not set to ignore the SYNC pin, any time SYNC is
taken low to put the part into holdover, the distribution outputs
turn off. The channel divider ignore SYNC function is found in
0x191[6], 0x194[6], 0x197[6], and 0x19A[6] for Channel
Divider 0, Channel Divider 1, Channel Divider 2, Channel Divider 3,
respectively.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappeared.
A flow chart of the automatic/internal holdover function
operation is shown in Figure 44.
AD9520-4