AD9520-4 Analog Devices, Inc., AD9520-4 Datasheet

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... GHz. An external 3.3 V/5 V VCO/VCXO 2.4 GHz can also be used. 1 The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-4 is used referring to that specific member of the AD9520 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...

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... AD9520-4 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 9 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ...................................................................... 10 Clock Output Absolute Phase Noise (Internal VCO Used Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...

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... Using the AD9520 Outputs for ADC Clock Applications .... 82   LVPECL Clock Distribution ...................................................... 82   CMOS Clock Distribution ......................................................... 83   Outline Dimensions ........................................................................ 84   Ordering Guide ........................................................................... 84       Rev Page AD9520-4                         ...

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... AD9520-4 SPECIFICATIONS Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5. noted. Minimum (min) and maximum (max) values are given over full VS and T POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VS_DRV 2.375 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5 ...

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... Off 410 ps 530 ps 650 ps 770 ps 890 ps 1010 ps 1130 ps Register 0x019[5:3]; see Table 53 Off 370 ps 490 ps 610 ps 730 ps 850 ps 970 ps 1090 ps Rev Page AD9520-4 is possible possible < VCP − 0 the voltage on the CP (charge CP CP < VCP − 0 VCP/2 V ...

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... AD9520-4 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in ...

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... VCO frequency or the frequency at the CLK inputs, depending on the AD9520 configuration Single-ended; termination = 10 pF MHz See Figure load, VS_DRV = 3.3 V/2 load, VS_DRV = 3.3 V/2 load, VS_DRV = 3 load, VS_DRV = 3 load, VS_DRV = 2 load, VS_DRV = 2.5 V AD9520-4 ...

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... AD9520-4 TIMING CHARACTERISTICS Table 5. Parameter LVPECL OUTPUT RISE/FALL TIMES Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUTPUT PECL For All Divide Values Variation with Temperature 1 OUTPUT SKEW, LVPECL OUTPUTS LVPECL Outputs That Share the Same Divider ...

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... Timing Diagrams t CLK CLK t PECL t CMOS Figure 2. CLK/ CLK to Clock Output Timing, Div = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 4. CMOS Timing, Single-Ended Load AD9520-4 ...

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... AD9520-4 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, OUTPUT = 1 GHz Divider = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset ...

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... S 360 f rms S Rev Page AD9520-4 Test Conditions/Comments Internal VCO; direct-to-LVPECL output and for loop bandwidths < 1 kHz Test Conditions/Comments Application example based on a typical setup where the reference source is clean wider PLL loop bandwidth is used; reference = 15.36 MHz ...

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... AD9520-4 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER LVPECL = 245.76 MHz; PLL LBW = 125 Hz LVPECL = 122.88 MHz; PLL LBW = 125 Hz LVPECL = 61.44 MHz; PLL LBW = 125 Hz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11 ...

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... AD9520, which is due to the internal pull-up resistor 2 pF SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I 2.0 V 0.8 V 110 μA 1 μ 2 μA 1 μ 2 MHz Rev Page AD9520 mode ...

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... AD9520-4 SERIAL CONTROL PORT—I²C MODE Table 14. Parameter SDA, SCL (WHEN INPUTS) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 VS and 0.9 VS Hysteresis of Schmitt Trigger Inputs Pulse width of Spikes That Must Be Suppressed by the Input Filter SDA (WHEN OUTPUTTING DATA) ...

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... On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.02 MHz Frequency above which the monitor indicates the presence of the reference 8 kHz Frequency above which the monitor indicates the presence of the reference 1.6 V 260 mV Rev Page AD9520-4 ...

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... AD9520-4 POWER DISSIPATION Table 18. Parameter POWER DISSIPATION, CHIP Power-On Default PLL Locked; One LVPECL Output Enabled PLL Locked; One CMOS Output Enabled Distribution Only Mode; VCO Divider On; One LVPECL Output Enabled Distribution Only Mode; VCO Divider Off; One LVPECL Output Enabled ...

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... See the Thermal Performance section for more details. −0 0.3 V −0 0.3 V Table 20. Package Type 64-Lead LFCSP (CP-64-4) ESD CAUTION −0 0.3 V −0 0.3 V −0 0.3 V 150°C −65°C to +150°C 300°C Rev Page AD9520-4 θ Unit JA 22 °C/W ...

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... AD9520-4 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REFMON STATUS REF_SEL BYPASS SCLK/SCL NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. Table 21. Pin Function Descriptions Input/ Pin Pin No. Output Type Mnemonic 1, 11, 12, I Power VS 32, 40, 41, 49, 57, 60 3.3 V CMOS REFMON 3 O 3.3 V CMOS ...

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... CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL output single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVPECL Output single-ended CMOS output. Rev Page AD9520-4 ...

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... AD9520-4 Input/ Pin Pin No. Output Type Mnemonic 47 O LVPECL or OUT3 (OUT3B) CMOS 48 O OUT3 (OUT3A) LVPECL or CMOS 50 O LVPECL or OUT2 (OUT2B) CMOS 51 O LVPECL or OUT2 (OUT2A) CMOS 52 O LVPECL or OUT1 (OUT1B) CMOS 53 O LVPECL or OUT1 (OUT1A) CMOS 55 O LVPECL or OUT0 (OUT0B) ...

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... PUMP 0.5 1.0 1.5 2.0 2.5 VOLTAGE ON CP PIN (V) Figure 9. Charge Pump Characteristics @ VCP = 3 PUMP DOWN 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 10. Charge Pump Characteristics @ VCP = 5.0 V –140 –145 –150 –155 –160 –165 –170 0 PFD FREQUENCY (MHz) AD9520-4 3 PUMP UP 4.0 4 100 ...

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... AD9520-4 –208 –210 –212 –214 –216 –218 DIFFERENTIAL INPUT –220 –222 SINGLE-ENDED INPUT –224 0 0.2 0.4 0.6 0.8 INPUT SLEW RATE (V/ns) Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/ REFIN 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.45 1.50 1.55 1.60 1.65 FREQUENCY (GHz) Figure 13. VCO Tuning Voltage vs. Frequency 0 –10 –20 –30 –40 –50 –60 –70 –80 – ...

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... Figure 23. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 1450 MHz Rev Page AD9520-4 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) 2pF 10pF 20pF 100 200 300 400 500 600 FREQUENCY (MHz) 10k ...

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... AD9520-4 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 1k 10k 100k 1M FREQUENCY (Hz) Figure 24. Internal VCO Phase Noise (Absolute) Direct-to-LVPECL @ 1625 MHz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 1k 10k 100k 1M FREQUENCY (Hz) Figure 25. Internal VCO Phase Noise (Absolute) Direct-to-LVPECL @ 1800 MHz – ...

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... Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz Rev Page INTEGRATED RMS JITTER (12kHz TO 20MHz): 442 1k 10k 100k 1M 10M FREQUENCY (Hz) 1k 10k 100k 1M 10M FREQUENCY (Hz) AD9520 100M 100M ...

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... AD9520-4 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...

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... N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 34. Rev Page AD9520-4 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 ...

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... AD9520-4 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 49 to Table 60). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. Once the desired ...

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... DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 35. Internal VCO and Clock Distribution (Mode 0) Rev Page AD9520-4 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV ...

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... AD9520-4 Mode 1: Clock Distribution or External VCO <1600 MHz When the external clock source to be distributed or the external VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. Bypassing the VCO divider limits the frequency of the clock source to < ...

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... DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Figure 36. Clock Distribution or External VCO < 1600 MHz (Mode 1) Rev Page AD9520-4 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV ...

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... AD9520-4 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6) ...

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... N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE DIVIDE Rev Page AD9520-4 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV OUT0 OUT0 ...

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... AD9520-4 Phase-Locked Loop (PLL) REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL REFIN STATUS BUF REFIN LOW DROPOUT BYPASS REGULATOR (LDO) LF CLK CLK The AD9520 includes an on-chip PLL with an on-chip VCO. The PLL blocks can be used either with the on-chip VCO to create a complete phase-locked loop or with an external VCO or VCXO ...

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... PLL is powered down. The single-ended buffers power down when the PLL is powered down, or when their respective individual power down registers are set. When the differential mode is selected, the single-ended inputs are powered down. Rev Page AD9520 ...

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... AD9520-4 In differential mode, the reference input pins are internally self- biased so that they can be ac-coupled via capacitors possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side ( REFIN ) should be decoupled via a suitable capacitor to a quiet ground. ...

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... FD 12 120 DM 12 120 DM 13 130 DM Rev Page AD9520-4 ). The SYNC pin reset is disabled by default. Notes (bypassed (bypassed and and and and ...

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... AD9520-4 Digital Lock Detect (DLD) By selecting the proper output through the mux on each pin, the DLD function is available at the LD, STATUS, and REFMON pins. The digital lock detect circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold) ...

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... PLL losing the reference clock; therefore, the holdover /C) of function puts the charge pump into a high impedance state to LEAK maintain the VCO frequency as close as possible to the original frequency before the reference clock disappeared. A flow chart of the automatic/internal holdover function operation is shown in Figure 44. Rev Page AD9520-4 ...

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... AD9520-4 PLL ENABLED DLD == LOW YES WAS LD PIN == HIGH WHEN DLD WENT LOW? YES HIGH IMPEDANCE CHARGE PUMP YES REFERENCE EDGE AT PFD? YES RELEASE CHARGE PUMP HIGH IMPEDANCE YES DLD == HIGH The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode ...

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... VCO STATUS A/B PROGRAMMABLE PRESCALER COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE FROM CHANNEL DIVIDER Figure 45. Reference and VCO Status Monitors Rev Page AD9520-4 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS VS_DRV ...

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... AD9520-4 VCO Calibration The AD9520 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off a divided REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present ...

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... Both the R delay and the N delay inside the PLL can be programmed to compensate for the propagation delay from the PLL components to minimize the phase offset between the feedback clock and the reference input. Rev Page AD9520-4 AD9520 LOOP FILTER ZERO DELAY ...

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... AD9520-4 PLL LF DIVIDE CLK CLK 1 0 CLOCK DISTRI- BUTION DISTRIBUTION CLOCK MODE 0 (INTERNAL VCO MODE) Figure 47. Simplified Diagram of the Three Clock Distribution Operation Modes CLOCK DISTRIBUTION A clock channel consists of three LVPECL clock outputs or six CMOS clock outputs that share a common divider. A clock output consists of the drivers that connect to the output pins ...

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... Certain M and N values for a channel divider result in a non- 50% duty cycle. A non-50% duty cycle can also result with an even division ≠ N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Rev Page AD9520-4 for the Output Dividers X Low High Cycles M ...

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... AD9520-4 Duty-cycle correction requires the following channel divider conditions: • An even division must be set • An odd division must be set When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value 1)/( expressed as a percent. ...

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... SYNC operation by setting the no sync bit of the channel. Channels that are set to ignore SYNC (excluded channels) do not set their outputs static during a SYNC operation, and their outputs are not synchronized with those of the included channels. Rev Page AD9520-4 Figure 49 Figure 50 (the VCO divider not Figure 49 ...

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... AD9520-4 CHANNEL DIVIDER OUTPUT CLOCKING INPUT TO VCO DIVIDER INPUT TO CHANNEL DIVIDER SYNC PIN OUTPUT OF CHANNEL DIVIDER Figure 49. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input CHANNEL DIVIDER OUTPUT CLOCKING INPUT TO CLK INPUT TO CHANNEL DIVIDER SYNC PIN OUTPUT OF CHANNEL DIVIDER Figure 50. SYNC Timing Pipeline Delay When VCO Divider Is Not Used— ...

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... LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. The AD9520 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. Rev Page AD9520-4 ...

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... AD9520-4 When the AD9520 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). • The VCO is off. • The CLK input buffer is off, but the CLK input dc bias circuit is on. • In differential mode, the reference input buffer is off, but the dc bias circuit is still on. • ...

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... An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. Rev Page AD9520-4 Definition Start Repeated start Stop ...

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... AD9520-4 SDA MSB SCL SDA MSB = 0 SCL Figure 56. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration) MSB = 1 SDA SCL Figure 57. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration) No acknowledge bit: this bit is the ninth bit attached to any 8-bit data byte ...

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... Figure 58. I²C Serial Port Timing Rev Page RAM Address Low Byte A RAM Data 1 A RAM Data 2 A RAM Data 2 RAM RAM R A Data 0 A Data RISE SPIKE t t IDLE HLD; STR t SET; STP P AD9520 RAM A Data ...

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... AD9520-4 SPI SERIAL PORT OPERATION Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down kΩ ...

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... Table 44. Streaming Mode (No Addresses Are Skipped) Write Mode LSB first MSB first I11 I10 A11 = 0 A10 = Rev Page AD9520-4 Address Direction Stop Sequence Increment 0x230, 0x231, 0x232, stop Decrement 0x001, 0x000, 0x232, stop ...

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... AD9520-4 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 61. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE ...

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... Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 64 CLK t t HIGH LOW t DH BIT N BIT Figure 66. Serial Control Port Timing—Write Rev Page AD9520 ...

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... AD9520-4 EEPROM OPERATIONS The AD9520 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by customers to create and store a user-defined register setting file when power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. ...

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... This sequence permits the user with more discrete instructions that can be written to the EEPROM than would have otherwise been possible due to the limited size of the EEPROM buffer segment. It also permits the user to write the same register multiple times with a different value each time. Rev Page AD9520-4 ...

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... AD9520-4 Table 47. Example of EEPROM Buffer Segment Reg Addr (Hex) Bit 7 (MSB) Start EEPROM Buffer Segment 0xA00 0 0xA01 0xA02 0xA03 0 0xA04 0xA05 0xA06 0 0xA07 0xA08 0xA09 0xA0A Bit 6 Bit 5 Bit 4 Bit 3 Number of bytes [6:0] of first group of registers Address [15:8] of first group of registers Address [7:0] of first group of registers ...

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... A where T is the ambient temperature (°C). A Values of θ are provided for package comparison and PCB JC design considerations when an external heat sink is required. Values of Ψ JB design considerations. Rev Page AD9520-4 Value (°C/W) 22.0 19.2 17.2 11.6 1.3 0.1 can be used for a first-order JA by the equation J × PD) ...

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... AD9520-4 REGISTER MAP Register addresses that are not listed in Table 49 are not used, and writing to those registers has no effect. Writing to register addresses marked unused also has no effect. Table 49. Register Map Overview Addr (Hex) Parameter Bit 7 (MSB) Serial Port Configuration 000 Serial port config ...

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... CSDLD En OUT11 Unused Divider 0 low cycles Divider 0 Divider 0 Divider 0 ignore force start high SYNC high Unused Unused Rev Page AD9520-4 Bit 2 Bit 1 Bit 0 (LSB) Enable Enable Unused external zero delay zero delay REF2 REF1 freq > Digital lock freq > threshold detect ...

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... AD9520-4 Addr (Hex) Parameter Bit 7 (MSB) 193 Divider 1 (PECL) 194 Divider 1 bypass 195 196 Divider 2 (PECL) 197 Divider 2 bypass 198 199 Divider 3 (PECL) 19A Divider 3 bypass 19B 19C to 1DF VCO Divider and CLK Input 1E0 VCO divider 1E1 Input CLKs Unused ...

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... EEPROM Buffer Segment Register 16 (default: number of bytes for Group 6) EEPROM Buffer Segment Register 19 (default: number of bytes for Group 7) EEPROM Buffer Segment Register 22 (default: IO_UPDATE from EEPROM) EEPROM Buffer Segment Register 23 (default: end of data) Unused Rev Page AD9520-4 Bit 2 Bit 1 Bit 0 (LSB) Default Value ...

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... AD9520-4 Addr (Hex) Parameter Bit 7 (MSB) EEPROM Control B00 EEPROM status (read-only) B01 EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 6 Bit 5 Bit 4 Bit 3 Unused Unused Unused Unused Rev Page Bit 2 Bit 1 Bit 0 (LSB) Unused STATUS_ EEPROM ...

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... EEPROM. It does not affect AD9520 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with 0x005, allow the user to store a unique ID to identify which version of AD9520 register settings is stored in the EEPROM. It does not affect AD9520 operation in any way (default: 0x00). Rev Page AD9520 mode.) ...

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... AD9520-4 Table 53. PLL Reg. Addr (Hex) Bit(s) Name Description 010 [7] PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity [ [ positive (higher control voltage produces higher frequency; default). ...

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... N/A internal holdover comparator output (active high LVL VS (PLL power supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode DYN Selected reference to PLL (differential reference when in differential mode). Rev Page AD9520-4 ...

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... AD9520-4 Reg. Addr (Hex) Bit(s) Name Description [7] [6] [5] [ 017 [1:0] Antibacklash [1] pulse width 018 [7] Enable CMOS Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. ...

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... Selected reference (low = REF1, high = REF2 LVL DLD; active high LVL Holdover active (active high LVL N/A, do not use LVL VS (PLL supply DYN REF1 clock (differential reference when in differential mode). Rev Page AD9520-4 ...

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... AD9520-4 Reg. Addr (Hex) Bit(s) Name Description [5] [4] [ 01B [7] Enable VCO Enables or disables VCO frequency monitor. frequency [ disable VCO frequency monitor (default). monitor [ enable VCO frequency monitor. ...

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... AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency (active low LVL Selected reference (low = REF2, high = REF1 LVL DLD; active low LVL Holdover active (active low LVL N/A, do not use. Rev Page AD9520-4 ...

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... AD9520-4 Reg. Addr (Hex) Bit(s) Name Description 01D [7] Enable Enables the Status_EEPROM signal at the STATUS pin. Status_EEPROM [ the STATUS pin is controlled by 0x017[7:2] selection. at STATUS pin [ select Status_EEPROM signal at STATUS pin. This bit overrides 0x017[7:2] (default). 01D [6] Enable Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input. ...

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... Output Type X 0 (default) LVPECL X 1 LVPECL 0 (default) 0 CMOS 0 1 CMOS 1 0 CMOS 1 1 CMOS ). OD [2] V (mV 400 1 600 0 (default) 780 1 960 Rev Page AD9520-4 OUT0A OUT 0B Noninverting Inverting Inverting Noninverting Noninverting Noninverting Inverting Inverting Noninverting Inverting Inverting Noninverting ...

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... AD9520-4 Reg. Addr (Hex) Bit(s) Name Description 0F6 [7:0] OUT6 control This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. 0F7 [7:0] OUT7 control This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. ...

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... Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1). Bypasses and powers down the divider; routes input to divider output. [ use divider (default). [ bypass divider. Rev Page AD9520-4 ...

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... AD9520-4 Reg. Addr (Hex) Bit(s) Name 197 [6] Divider 2 ignore SYNC 197 [5] Divider 2 force high 197 [4] Divider 2 start high 197 [3:0] Divider 2 phase offset 198 [2] Channel 2 power-down 198 [1] Channel 2 direct-to-output 198 [0] Disable Divider 2 DCC 199 [7:4] Divider 3 low cycles 199 [3:0] Divider 3 high cycles ...

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... VCO as input to VCO divider; cannot bypass VCO divider when this is selected. This bit must be set to use the PLL with the internal VCO. Bypasses or uses the VCO divider. [ use VCO divider (default). [ bypass VCO divider; cannot select VCO as input when this is selected. Rev Page AD9520-4 Divide 2 (default ...

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... AD9520-4 Table 57. System Reg. Addr (Hex) Bit(s) Name 230 [3] Disable power-on SYNC 230 [2] Power-down SYNC 230 [1] Power-down distribution reference 230 [0] Soft SYNC Table 58. Update All Registers Reg. Addr (Hex) Bit(s) Name Description 232 [0] IO_UPDATE This bit must be set transfer the contents of the buffer registers into the active registers. This happens on the next SCLK rising edge. This bit is self-clearing ...

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... B03 [0] REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). [ setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process reset by the I²C master after the data transfer is done. Rev Page AD9520-4 ...

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... AD9520-4 APPLICATIONS INFORMATION FREQUENCY PLANNING USING THE AD9520 The AD9520 is a highly flexible PLL. When choosing the PLL settings and version of the AD9520, the following guidelines should be kept in mind. The AD9520 has four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider ...

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... The AD9520 offers LVPECL outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. Rev Page AD9520-4 60.4Ω (1.0 INCH) 10Ω CMOS CMOS MICROSTRIP Figure 71 ...

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... ORDERING GUIDE Model Temperature Range AD9520-4BCPZ 1 −40°C to +85°C 1 AD9520-4BCPZ-REEL7 −40°C to +85°C 1 AD9520-4/PCBZ RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.00 BSC SQ 0.60 MAX 49 48 ...